Filwizard simulink model error

10 views (last 30 days)
Abhishek Kumar
Abhishek Kumar on 23 May 2019
In a model for a synchronous system created by filwizard, why there are no ports of clk and rst visible?

Sign in to answer this question.

Answers (0)

Categories

Find more on HDL Verifier in Help Center and File Exchange

Tags

Products

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!