Hello, I've got a vivado project with added simulink-generated IP Core.
I'm always getting huge timing delays on the implimentation stage.
For test purposes, I've made a very simple simulink project with multipliers.
I'm exporting it with the following settings:
Adding it to the following block design:
Connecting clock enable to constant 1, reset to inverted reset, used in previous blocks (because the simulink generated IP Core uses inverted reset).
I'm getting the following result:
I've tried both generating HDL code and packaging it into IP Core by Vivado and generating IP Core directly from Simulink. The results are the same.
There are no timing errors If I don't use simulink generated IP core (or HDL code).
Is there some settings I've applied wrong?