System Generator: Virtex-6 ML605 design test using test vectors from MATLAB/file

Hi All,

I used System Generator to design an algorithm to be implemented on the ML605 evaluation board (Virtex-6).

I have the input test vectors in my MATLAB workspace. I performed a Hardware Co-simulation and verified the design using the single-stepped clock option instead of the free-running clock. But even while running on the FPGA, the design operates very slowly and not at the true clock speed.

Now, I need to test the FPGA with a real clock like at 100MHz. But the JTAG or even the Ethernet interface isn't fast enough to send input test vectors so fast. Correct me if I am wrong.

I can use chipscope for monitoring my outputs but how do I send the input test vectors from Simulink/MATLAB to the FPGA? Store in memory? How would I do that? Because storing in memory would mean operating at slower clock while transferring test vectors and then start the design with the true clock (100MHz) but as far as I know, we cannot change clocks in middle of a simulation.

Please help!

Thanks -Nik