SoC Blockset

Design, evaluate, and implement SoC hardware and software architectures

SoC Blockset™ provides Simulink^® blocks and visualization tools for modeling, simulating, and analyzing hardware and software architectures for ASICs, FPGAs, programmable systems-on-chip (SoCs), and multicore microcontrollers/microprocessors.

SoC Blockset lets you simulate memory and internal and external connectivity, as well as scheduling and OS effects, using generated test traffic or real I/O data. You can quickly explore different system architectures, estimate interface complexity for hardware and software partitioning, and evaluate software performance and hardware utilization.

When used with Embedded Coder and HDL Coder, SoC Blockset implements applications for Xilinx^® and Intel^® FPGAs, programmable SoCs such as Xilinx UltraScale+™ MPSoC and RFSoC devices, and multicore microcontrollers/microprocessors such as Texas Instruments C2000™ MCUs.

Get Started:

Simulate and Analyze SoC Architectures
Analyze System Performance
Deploy to SoC and FPGA Devices
Featured Applications
Simulate and Deploy to Microcontrollers and Microprocessors

Designing a Datapath from an FPGA to a Processor with SoC Blockset: Modeling and Simulation

Simulate and Analyze SoC Architectures

Develop and combine software algorithms, hardware logic, memory systems, and I/O devices into your SoC application. Evaluate architecture alternatives before deploying to hardware.

Develop SoC Architectures from Specifications

You can start with a functional architecture of your application in System Composer™, and allocate functional components to the SoC hardware architecture (processor), programmable logic (FPGA), and memory. Simulate the behavior of the entire application and verify its functional correctness. Then evaluate the implementation to decide how to allocate its functional components between hardware and software.

Systems Engineering Approach for SoC Applications

Allocate functional components to SoC hardware architecture components using System Composer.

Analyze Algorithm Resource Usage

Analyze Simulink models or MATLAB^® functions to generate reports summarizing the number of arithmetic operators required for implementation. Use these reports to compare different architectures for FPGA, ASIC, and SoC devices, perform design tradeoffs, and explore hardware/software partitioning.

Analyze Algorithm Resources

Estimate Number of Operators for MATLAB Algorithm

Compare FIR Filter Implementations Using socModelAnalyzer

View the estimated number and type of operators needed to implement MATLAB functions or Simulink models.

Memory Transactions

Model DDR memory and simulate shared memory transactions between hardware logic and embedded processors. Configure DMA memory controllers to arbitrate memory traffic. Account for memory latency and throughput in simulation.

Analyze Memory Bandwidth Using Traffic Generators

Streaming Data from Hardware to Software

Streaming Data from Software to Hardware

Memory and Register Data Transfers

External Memory Channel Protocols

Developing Radio Applications for RFSoC with MATLAB & Simulink (4 videos)

Designing a Datapath from an FPGA to a Processor with SoC Blockset: Modeling and Simulation

Task Execution

Model task execution of embedded software as managed by the operating system (OS). Simulate tasks with accurate timing, accounting for context switching, task preemption, and execution duration. Model software interrupts generated by FPGA fabric. Apply statistics to simulate nondeterministic task duration, or apply task durations recorded during hardware testing.

Concept of Task Execution

Task Manager

Task Execution

Task Duration

Triggering Software Tasks by FPGA Interrupts

Visualize task preemption, context switching, and execution duration with timing diagrams.

SoC Model Templates

Build complete models of SoC applications from scratch using a step-by-step approach, or start from predefined templates for hardware/software coprocessing, including templates for vision and communication applications.

Stream from FPGA to Processor Template

Stream from Processor to FPGA Template

Software-Defined Radio Template

HDMI Template

Frame Buffer with HDMI Template

RFSoC Template

Build models for SoC applications using predefined model templates.

Simulation with Recorded I/O Data

Record hardware peripheral sources such as RF signals or HDMI data, and then play back recordings as sources in simulations or hardware testing.

Record I/O Data from SoC Devices

Simulate with I/O Data Recorded from SoC Devices

Play back recordings as a source for simulation.

Analyze System Performance

Evaluate memory performance and task execution through simulation and perform on-device profiling.

Task Execution Analysis

Simulate the software system of SoC applications by running Simulink models that incorporate timer-driven and event-driven tasks. Visualize task execution timing, preemption, rate overruns, drops, and core utilization. Replay task executions in simulation using task timing data captured from previous simulations or directly from SoC devices.

Task Execution

The Task Execution report provides minimum, maximum, and typical timing of tasks as well as processor core usage statistics.

DDR Memory Performance

Analyze the memory bandwidth of system designs. Visualize simulation results and bandwidth metrics before deploying to the SoC device.

Diagnostic Information from FPGA Execution

Kernel Instrumentation Profiler

Simulate shared memory transactions and analyze performance.

On-Device Memory Performance Monitoring and Task Execution Profiling

Measure memory performance and task execution on an SoC device, and then visualize and analyze these measurements to tune an SoC model to meet your system performance requirements. Interact in real time with SoC devices from MATLAB or from your Simulink test bench.

Code Instrumentation Profiler

Profile Task Execution on Processor

Measure task execution with code instrumentation profiler.

Deploy to SoC and FPGA Devices

Generate reference designs and RTL code for programmable logic. Generate C/C++ code for processor tasks. Deploy complete hardware/software applications to development boards.

Generate Embedded Software Project

When used with Embedded Coder^®, SoC Blockset generates complete embedded software projects from models, including schedulers, software tasks, and I/O device driver integration.

Generate SoC Design

SoC Builder

Code Generation of Software Tasks

Generate complete embedded software projects from models.

Generate Reference Designs

Generate reference designs for programmable logic. Reference designs are configured networks of IP cores with data and control paths that may be connected to external memories and software applications. SoC Blockset connects to Xilinx and Intel design tools to produce bitstreams and then programs FPGA and SoC boards.

Export Custom Reference Design from SoC Model

Export Custom Reference Design

Generate reference designs for use with HDL algorithm IP generated using HDL Coder.

Target COTS Boards and Custom Boards

Implement hardware/software applications on supported hardware kits including Xilinx Zynq UltraScale+ MPSoCs and RFSoCs, Zynq-7000 SoCs and Intel Cyclone and Arria SoC FPGAs. Target boards using hardware support packages or build support for custom boards.

Transmit and Receive a Tone Using Xilinx RFSoC Device - Part 1 System Design

Transmit and Receive a Tone Using Xilinx RFSoC Device - Part 2 Deployment

5G NR Cell Search Using Xilinx RFSoC Device

Supported Third-Party Tools and Hardware

SoC Blockset Support Package for Xilinx Devices

SoC Blockset Support Package for Intel Devices

Designing a Datapath from an FPGA to a Processor with SoC Blockset: Xilinx Deployment (5:43)

Explore gallery (4 images).

Featured Applications

Develop and deploy hardware/software applications for wireless communications, video and image processing, and controls.

Wireless Communications and Radar

Evaluate wireless communications and radar applications while accounting for the effects of processor, FPGA and DDR memory subsystems. Use predefined models of Xilinx Zynq UltraScale+ MPSoC and RFSoC devices to simulate hardware/software applications, then deploy to development boards and configure the data converters of RFSoC devices.

Pulse-Doppler Radar Using Xilinx RFSoC Device

5G NR MIB Recovery Using Xilinx RFSoC Device

OFDM Transmit and Receive Using Xilinx RFSoC Device

Use SoC Blockset to model, simulate, and deploy applications like range Doppler radars targeted to Xilinx UltraScale+ RFSoCs.

Video and Image Processing

Data-intensive video and image processing applications require designers to assess memory bandwidth requirements to ensure the application’s frame rate and frame size requirements are met. Use SoC Blockset to model external DDR memory and evaluate memory bandwidth dynamically with simulation. Then generate the fully-compliant AXI4 interface IP using HDL Coder™.

Vertical Video Flipping Using External Memory

Contrast Limited Adaptive Histogram Equalization with External Memory

Modeling a video application using SoC Blockset blocks.

Motor and Power Control

Implement real-time motor and power electronics control on multicore microcontrollers or SoCs by partitioning control tasks into different computing units. Simulate the ADC/PWM peripheral/inter-processor communication with plant and deploy to prototype systems.

Partition Motor Control for Multiprocessor MCUs

Integrate MCU Scheduling and Peripherals in Motor Control Application

Partition algorithms between multiple processors.

Simulate and Deploy to Microcontrollers and Microprocessors

Develop software algorithms, incorporating effects of operating system and hardware components, then deploy to hardware.

Peripheral Modeling

Perform closed-loop simulations that include the behavior of peripherals such as ADCs and PWMs. Models can account for ADC-PWM synchronization and latency.

Integrate MCU Scheduling and Peripherals in Motor Control Application

ADC Interface

PWM Interface

Adding MCU Peripheral Modeling in Motor Control Using SoC Blockset (8:02)

Adding MCU Peripheral Modeling in Motor Control Using SoC Blockset

Multiprocessor Architecture Modeling

Partition algorithms between multiple processors to achieve design modularity and to improve performance. Model multiprocessor execution and inter-processor data communication.

Interprocess Data Communication via Dedicated Hardware Peripheral

Partition Motor Control for Multiprocessor MCUs

Multicore Motor Control Using SoC Blockset

Deploy to Microcontroller and Microprocessor Boards

Perform rapid prototyping on hardware boards by generating software applications with Embedded Coder. Perform on-device profiling to fine-tune applications.

Texas Instruments C2000 Support from SoC Blockset

Embedded Linux Support from SoC Blockset

Get Started with SoC Blocks on MCUs

Support Your Embedded Linux Board in the SoC Blockset