Many engineers test their algorithm models in simulation. Through simulation they identify design and requirement errors in their model before generating production code. However, eliminating design errors remains a challenge and extensive testing with 100 percent coverage may still result in a design that contains robustness errors such as overflows and divide-by-zero. Some of these errors may reveal themselves under rare conditions and could be time consuming to debug. They may be induced by certain calibration values and only be found on the HIL bench or in a test vehicle. This presentation illustrates a method for detecting and eliminating such design errors using Simulink Design Verifier™.
Recorded: 13 May 2014
Select a Web Site
Choose a web site to get translated content where available and see local events and offers. Based on your location, we recommend that you select: .Select web site
You can also select a web site from the following list:
Select the China site (in Chinese or English) for best site performance. Other MathWorks country sites are not optimized for visits from your location.