Design Shift-Left for Early Digital Design and HDL

Increasing performance requirements and manufacturing variation are driving greater complexity in high-speed mixed-signal systems such as 112+ Gb/s SerDes. As analog and digital subsystems become more tightly coupled, development cycles lengthen and design risks increase. This paper presents a shift-left workflow that enables early digital algorithm development, refinement, verification, and automatic HDL generation within a high-level SerDes system model. Using a decision feedback equalizer (DFE) adaptation algorithm as a case study, we demonstrate a workflow that transforms a high-level algorithm into synthesizable HDL while enabling continuous system-level validation throughout development.

This paper was presented at DesignCon 2025.