High-Level Hardware Design
Design your subsystem by choosing from more than 300 HDL-ready Simulink blocks and MATLAB functions; add Stateflow charts, Simscape models, and deep learning networks. Simulate the hardware behavior of your design, explore alternative architectures, and generate synthesizable Verilog, SystemVerilog, or VHDL using fixed-point or floating-point data types or a combination of both.
Explore a wide variety of hardware architecture and fixed-point quantization options before committing to an RTL implementation. Use high-level synthesis optimizations such as resource sharing, pipelining, and delay balancing, that efficiently map to device resources such as logic, DSPs, and RAMs.
Use with HDL Verifier to ensure your generated RTL will function as required in its system context. Verify generated HDL with MATLAB and Simulink testbenches using cosimulation with leading HDL simulators. Use FPGA-in-the-loop testing to verify your design’s implementation on FPGA development boards.
“Simulink helps system architects and hardware designers communicate. It is like a shared language that enables us to exchange knowledge, ideas, and designs. Simulink and HDL Coder enable us to focus on developing our algorithms and refining our design via simulation, not on checking VHDL syntax and coding rules.”Marcel van Bakel, Philips Healthcare