CIC Interpolator

Interpolate signal using CIC filter

Since R2022a

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Libraries:
DSP HDL Toolbox / Filtering

Description

The CIC Interpolator block interpolates an input signal by using a cascaded integrator-comb (CIC) interpolation filter. CIC interpolation filters are a class of linear phase finite impulse response (FIR) filters consisting of a comb part and an integrator part. The CIC interpolation filter structure consists of N sections of cascaded comb filters, a rate change factor of R, and N sections of cascaded integrators. For more information about CIC interpolation filters, see Algorithms.

The block supports these combinations of input and output data.

• Scalar input and scalar output — Support for fixed and variable interpolation rates

• Scalar input and vector output — Support for fixed interpolation rates only

• Vector input and vector output — Support for fixed interpolation rates only

The block provides an architecture suitable for HDL code generation and hardware deployment.

Note

You can also generate HDL code for this hardware-optimized algorithm, without creating a Simulink^® model, by using the DSP HDL IP Designer app. The app provides the same interface and configuration options as the Simulink block.

Examples

Implement CIC Interpolator Filter for HDL

Filter and upsample data by using the CIC Interpolator block.

• Open Script

Implement Digital Upconverter for FPGA

Design a digital upconverter (DUC) for LTE on FPGAs.

• Open Script

Ports

Input

data — Input data

scalar | column vector

Input data, specified as a scalar or a column vector with a length from 1 to 64. The input data must be a signed integer or signed fixed point with a word length less than or equal to 32.

While processing the input data, the block implements the rounding method Floor and the overflow action Wrap. For more details, see Rounding Modes and Overflow Handling.

Data Types: int8 | int16 | int32 | signed fixed point
Complex Number Support: Yes

valid — Indicates valid input data

scalar

Control signal that indicates if the input data is valid. When valid is 1 (true), the block captures the values from the input data port. When valid is 0 (false), the block ignores the values from the input data port.

Data Types: Boolean

R — Variable interpolation rate

scalar

Use this port to dynamically specify the variable interpolation rate during run time.

This value must have the data type fixdt(0,12,0) and must be an integer in the range from 1 to the Interpolation factor (Rmax) parameter value.

Dependencies

To enable this port, on the Main tab, set the Interpolation factor source parameter to Input port.

Data Types: fixdt(0,12,0)

reset — Clears internal states

scalar

Control signal that clears internal states. When reset is 1 (true), the block stops the current calculation and clears internal states. When the reset is 0 (false) and the input valid is 1 (true), the block captures data for processing.

For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.

Dependencies

To enable this port, on the Control Ports tab, select the Enable reset input port parameter.

Data Types: Boolean

Output

data — CIC-interpolated output data

scalar | column vector

CIC-interpolated output data, returned as a scalar or a column vector with a length from 1 to 64. You can define the data type of this output by setting the Output data type parameter on the Data Types tab.

Data Types: int8 | int16 | int32 | signed fixed point
Complex Number Support: Yes

valid — Indicates valid output data

scalar

Control signal that indicates if the data from the output data port is valid. When valid is 1 (true), the block returns valid data from the output data port. When valid is 0 (false), the values from the output data port are not valid.

Data Types: Boolean

ready — Indicates block is ready for new input data

scalar

Control signal that indicates that the block is ready for new input data sample on the next cycle. When ready is 1 (true), you can specify the data and valid inputs for the next time step. When ready is 0 (false), the block ignores any input data in the next time step.

Data Types: Boolean

Parameters

Main

Interpolation factor source — Source of interpolation factor

Property (default) | Input port

Select whether the block operates with a fixed or variable interpolation rate.

• Property — Use a fixed interpolation rate specified from the Interpolation factor (R) parameter.

• Input port — Use a variable interpolation rate specified from the R input port.

Note

The block does not support variable interpolation for these two combinations of input and output:

• Scalar input and vector output

• Vector input and vector output

Interpolation factor (R) — Interpolation factor

2 (default) | integer from 1 to 2048

Specify the interpolation factor rate at which the block interpolates the input. This value must be an integer. The range of available values depends on the type of input and output data.

Input Data	Output Data	Interpolation factor (R) Valid Values
Scalar	Scalar	Integer from 1 to 2048
Scalar	Vector	Integer from 1 to 64
Vector	Vector	Integer from 1 to 64

Note

For vector inputs, select the interpolation factor rate and input vector length such that their multiplication value does not exceed 64.

Dependencies

To enable this parameter, set the Interpolation factor source parameter to Property.

Interpolation factor (Rmax) — Upper bound of variable interpolation factor

2 (default) | integer from 1 to 2048

Specify the upper bound of the range of valid values for the R input port.

Note

The block does not support variable interpolation for these two combinations of input and output:

• Scalar input and vector output

• Vector input and vector output

Dependencies

To enable this parameter, set the Interpolation factor source parameter to Input port.

Differential delay (M) — Differential delay

1 (default) | 2

Specify the differential delay of the comb part of the block.

Number of sections (N) — Number of integrator and comb sections

2 (default) | 1 | 3 | 4 | 5 | 6

Specify the number of sections in either the comb part or the integrator part of the block.

Minimum number of cycles between valid input samples — Minimum number of cycles between valid input samples

1 (default) | factors or multiples of R

Specify the minimum number of cycles between the valid input samples as 1, factors of R, or multiples of R based on the type of input and output data, where R is the interpolation factor.

Input Data	Output Data	Minimum Number of Cycles Between Valid Input Samples
Scalar	Scalar	greater than or equal to R
Scalar	Vector	factors less than R
Vector	Vector	1

Dependencies

To enable this parameter, set the Interpolation factor source parameter to Property.

Gain correction — Output gain compensation

off (default) | on

Select this parameter to compensate for the output gain of the block.

The latency of the block changes depending on the type of input, the interpolation you specify, the number of sections, and the value of this parameter. For more information on the latency of the block, see Latency.

Data Types

Output data type — Data type of output

Full precision (default) | Same word length as input | Minimum section word lengths

Select the data type for the output data.

• Full precision — The output data type has a word length equal to the input word length plus gain bits.

• Same word length as input — The output data type has a word length equal to the input word length.

• Minimum section word lengths — The output data type uses the word length you specify in the Output word length parameter.

Output word length — Word length of output

16 (default) | integer from 2 to 104

Specify the word length of the output as an integer from 2 to 104.

Dependencies

To enable this parameter, set the Output data type parameter to Minimum section word lengths.

Control Ports

Enable reset input port — Option to enable reset input port

off (default) | on

Select this parameter to enable the reset input port. The reset signal implements a local synchronous reset of the data path registers.

For more reset considerations, see Tips.

Use HDL global reset — Option to connect data path registers to generated HDL global reset signal

off (default) | on

Select this parameter to connect the generated HDL global reset signal to the data path registers. This parameter does not change the appearance of the block or modify simulation behavior in Simulink. When you clear this parameter, the generated HDL global reset clears only the control path registers. The generated HDL global reset can be synchronous or asynchronous depending on the HDL Code Generation > Global Settings > Reset type parameter in the model Configuration Parameters.

For more reset considerations, see Tips.

Tips

Reset Behavior

• By default, the CIC Interpolator block connects the generated HDL global reset to only the control path registers. The two reset parameters, Enable reset input port and Use HDL global reset, connect a reset signal to the data path registers. Because of the additional routing and loading on the reset signal, resetting data path registers can reduce synthesis performance.

• The Enable reset input port parameter enables the reset port on the block. The reset signal implements a local synchronous reset of the data path registers. For optimal use of FPGA resources, this option does not connect the reset signal to registers targeted to the DSP blocks of the FPGA.

• The Use HDL global reset parameter connects the generated HDL global reset signal to the data path registers. This parameter does not change the appearance of the block or modify simulation behavior in Simulink. The generated HDL global reset can be synchronous or asynchronous depending on the HDL Code Generation > Global Settings > Reset type parameter in the model Configuration Parameters. Depending on your device, using the global reset might move registers out of the DSP blocks and increase resource use.

• When you select the Enable reset input port and Use HDL global reset parameters together, the global and local reset signals clear the control and data path registers.

Reset Considerations for Generated Test Benches

• FPGA-in-the-loop (FIL) initialization provides a global reset but does not automatically provide a local reset. With the default reset parameters, the data path registers that are not reset can result in FIL mismatches if you run the FIL model more than once without resetting the board. Select Use HDL global reset to reset the data path registers automatically, or select Enable reset input port and assert the local reset in your model so the reset signal becomes part of the Simulink FIL test bench.

• The generated HDL test bench provides a global reset but does not automatically provide a local reset. With the default reset parameters and the default register reset Configuration Parameters, the generated HDL code includes an initial simulation value for the data path registers. However, if you are concerned about X-propagation in your design, you can set the HDL Code Generation > Global Settings > Coding style > No-reset register initialization parameter in Configuration Parameters to Do not initialize. In this case, with the default block reset parameters, the data path registers that are not reset can cause X-propagation on the data path at the start of HDL simulation. Select Use HDL global reset to reset the data path registers automatically, or select Enable reset input port and assert the local reset in your model so the reset signal becomes part of the generated HDL test bench.

Algorithms

CIC Interpolation Filter

The transfer function of a CIC interpolation filter is

$$\begin{array}{l}H(z)={\left[{\displaystyle \sum _{k=0}^{RM-1}{z}^{-k}}\right]}^N=\frac{{(1-z^{-RM})}^N}{{(1-z^{-1})}^N}=\frac{{(1-z^{-RM})}^N}{1}·\frac{1}{{(1-z^{-1})}^N}=H_{\text{C}}{}^N(z)·H_{\text{I}}{}^N(z).\\ \end{array}$$

• H_C is the transfer function of the comb part of the CIC filter.

• H_I is the transfer function of the integrator part of the CIC filter.

• N is the number of sections in either the comb part or integrator part of the filter. This value does not represent the total number of sections throughout the entire filter.

• R is the interpolation factor.

• M is the differential delay.

CIC Filter Structure

The CIC Interpolator block has the CIC filter structure shown in this figure. The structure consists of N sections of cascaded comb filters, a rate change factor of R, and N sections of cascaded integrators [1].

You can locate the unit delay in the integrator part of the CIC filter in either the feedforward or feedback path. These two configurations yield an identical filter frequency response. However, the numerical outputs from these two configurations are different due to the latency of the block. Because this configuration is preferred for HDL implementation, this block puts the unit delay in the feedforward path of the integrator.

Fixed and Variable Interpolation

The block upsamples the comb stage output using R, either using the fixed interpolation rate provided using the Interpolation factor (R) parameter or the variable interpolation rate provided using the R input port. At the upsampling stage, the block uses a counter to count the valid input samples, which depend on the interpolation rate. Whenever the interpolation rate changes, the block resets and starts a new calculation from the next sample. This mechanism prevents the block from accumulating false values. Then, the block provides the interpolated output to the integrator part of the CIC filter.

Gain Correction

The gain of the CIC interpolation filter at each stage is given by

$$G_i=\left\{\begin{array}{cc}{2}^i& i=1,2,\mathrm{...},N\\ \frac{2^{2N-i}{\left(RM\right)}^{i-N}}{R}& i=N+1,\mathrm{...},2N\end{array}\right\}.$$

• G_i is the gain at ith stage.

• R is the Interpolation factor (R) parameter value.

• M is the Differential delay (M) parameter value.

• N is the Number of sections (N) parameter value.

The output of the block is amplified by a specific gain value. This gain equals the gain of the 2Nth stage of the CIC interpolation filter and is given by $$Gain=\frac{{(R\text{x}M)}^N}{R}$$.

The block implements gain correction in two parts: coarse gain and fine gain. In coarse gain correction, the block calculates the shift value, adds the shift value to the fractional bits to create a numeric type, and performs a bit-shift left and reinterpretcast. In fine gain correction, the block divides the remaining gain with the coarse gain if the gain is not a power of 2. Then, the block multiplies the corrected coarse gain value by the inverse value of the fine gain. Before the block starts processing, all possible shift and fine gain values are precalculated and stored in an array.

You can modify this equation to $$Gain=2^{cGain}\text{x}fGain$$. In this equation, cGain is the coarse gain and fGain is the fine gain. These gains are given by these equations.

• $$cGain=floor({\log }_{2}Gain)$$

• $$fGain=Gain/2^{cGain}=Gain\text{x}{2}^{-cGain}{}^{}$$

To perform gain correction when the Interpolation factor source parameter is set to Input port, the block sets the output data type configured with the maximum interpolation rate and bit-shifts left for all of the values under the maximum interpolation rate. The bit-shift value is equal to $$Maximumgain-{\log }_2(currentgain)$$.

Output Data Type

The block outputs data based on the output data type selection. Consider a block with R, M, and N values of 8, 1, and 3, respectively, and an input width of 16. The word length at the ith internal stage is calculated as $$B_i=B_{\text{In}}+[{\log }_2(G_i)]$$, where:

• G_i is the gain at ith stage.

• B_In is the input word length.

• B_i is the word length at ith stage.

The output word length is calculated as $$B_{Out}=B_{In}+N-1$$, where B_Out is the output word length.

When you set the Output data type parameter to Full precision, the block outputs data with a word length of 22 by adding 6 gain bits to the input word length of 16. The word lengths of the internal comb and integrator stages are set to accommodate the bit growth.

When you set the Output data type parameter to Same word length as input, the block outputs data with a word length of 16, which is the same length as the input word length. The word lengths of the internal comb and integrator stages are set in the same way as in Full precision mode.

When you set the Output data type parameter to Minimum section word lengths and the Output word length parameter to 16, the block outputs data with a word length of 16. The word lengths of the internal comb and integrator stages are set in the same way as in Full precision mode.

Latency

The latency of the block changes depending on the type of input, the interpolation you specify, the number of sections, the value of the Gain correction parameter, and the value of the Minimum number of cycles between valid input samples parameter. This table shows the latency of the block. N is the number of sections, vecLen is the length of the vector, and R is the interpolation factor.

Common latency is equal to 2 + (N x (vecLen x R)) + 3 x N, when R is equal to 1 and is equal to 3 + (N x (vecLen x R)) + 3 x N, when R is greater than 1.

Input Data	Output Data	Interpolation Type	Gain Correction	Minimum number of cycles between valid input samples (NumCycles)	Latency in Clock Cycles
Scalar	Scalar	Fixed	off	NumCycles = R and > R	3 + N. 2 + N, when R = 1.
			on	NumCycles = R and > R	3 + N + 9. 2 + N + 9, when R = 1.
Scalar	Scalar	Variable	off	NA	3 + N + 2 x Rmax. 2 + N, when Rmax = 1.
			on	NA	2 + N + 2 x Rmax + 9. 2 + N + 9, when Rmax = 1.
Scalar	Vector	Fixed	off	NumCycles = 1	Common latency + 1, when R is greater than N. Common latency, when R is less than or equal to N. Common latency – (1 + floor(N/(3 x R))), when R is less than N and (vecLen == 2 && (R == 2 && (N == 4 || N == 5 || N == 6)) || (R== 3 && N == 6)).
				NumCycles < R	3 + N + ((R + 1) x N + 2) + 1 + (N – 1) x NumCycles.
			on	NumCycles = 1	Common latency + 1 + 9, when R is greater than N. Common latency + 9, when R is less than or equal to N. Common latency – (1 + floor(N/(3 x R))) + 9, when R is less than N and (vecLen == 2 && (R == 2 && (N == 4 || N == 5 || N == 6)) || (R == 3 && N == 6)).
				NumCycles < R	3 + N + ((R + 1) x N + 2) + 1 + (N – 1) x NumCycles + 9.
Vector	Vector	Fixed	off	NumCycles = 1	Common latency Common latency – 1, when (vecLen == 2 && (R == 2 && (N == 4 || N == 5 || N == 6)) || (R== 3 && N == 6)) || (vecLen == 3 && (R == 2 && N == 6)). Common latency – ((N >1) + (N > 4)), when R = 1 and vecLen == 2. Common latency – ((N > (vecLen – 1)), when R = 1 and vecLen > 2.
			on	NumCycles = 1	Common latency + 9. Common latency – 1 + 9, when (vecLen == 2 && (R == 2 && (N == 4 || N == 5 || N == 6)) || (R== 3 && N == 6)) || (vecLen == 3 && (R == 2 && N == 6)). Common latency – ((N >1) + (N > 4)) + 9, when R = 1 and vecLen == 2. Common latency – ((N > (vecLen – 1)) + 9, when R = 1 and vecLen > 2.

Note

The block does not support variable interpolation for these two combinations of input and output:

• Scalar input and vector output

• Vector input and vector output

Scalar Input

This section shows the output of the block for a scalar input with different R, M, and N values.

This figure shows the output of the block with the default configuration (that is, with a fixed interpolation rate and R, M, and N values of 2, 1, and 2, respectively). The latency of the block is 5 clock cycles and is calculated as 3 + N, where N is the number of sections.

This figure shows the output of the block with a fixed interpolation rate, R, M, and N values of 8, 1, and 3, respectively, and the Gain correction parameter selected. The latency of the block is 15 clock cycles and is calculated as 3 + N + 9, where N is the number of sections.

This figure shows the output of the block with variable interpolation rate (R input port) values of 2, 4, and 8 and with M and N values of 1 and 3, respectively. In this case, the Gain correction parameter is cleared. The block accepts R port value changes only when the valid input port is 1. The latency of the block is 22 clock cycles and is calculated as 3 + N + 2 x R_max, where N is the number of sections and R_max is the maximum interpolation factor.

Vector Input

This section shows the output of the block for a vector input with different R, M, and N values.

This figure shows the output of the block for a two-element column vector input with the default configuration (that is, with a fixed interpolation rate and R, M, and N values of 2, 1, and 2, respectively). The latency of the block is 17 clock cycles.

This figure shows the output of the block for an eight-element column vector input with a fixed interpolation rate, R, M, and N values of 8, 1, and 3, respectively, and the Gain correction parameter selected. The latency of the block is 213 clock cycles.

Performance

The performance of the synthesized HDL code varies with your target and synthesis options. It also varies based on the input data type.

This table shows the resource and performance data synthesis results of the block for a scalar input with fixed and variable interpolation rates and for a two-element column vector of type fixdt(1,16,0) with a fixed interpolation rate when R, M, and N are 2, 1, and 2, respectively. The generated HDL code is targeted to the AMD^® Zynq^®- 7000 ZC706 Evaluation Board.

Input Data	Interpolation Type	Slice LUTs	Slice Registers	Maximum Frequency in MHz
Scalar	Fixed rate	68	90	844.12
	Variable rate	143	115	451.83
Vector	Fixed rate	480	921	376.51

The resources and frequencies vary based on the type of input data, R, M, and N values, and other parameter values selected in the block mask. Using a vector input can increase the throughput, however, doing so also increases the number of hardware resources that the block uses.

References

[1] Hogenauer, E. “An Economical Class of Digital Filters for Decimation and Interpolation.” IEEE Transactions on Acoustics, Speech, and Signal Processing 29, no. 2 (April 1981): 155–62. https://doi.org/10.1109/TASSP.1981.1163535.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Version History

Introduced in R2022a