FPGA Data Capture

Capture data to MATLAB or Simulink from RFSoC devices

Capture raw data using FPGA input and output (IO) application programming interface (API) from the Xilinx^® Zynq^® UltraScale+™ ZCU111 evaluation kit or Xilinx Zynq UltraScale+ ZCU216 evaluation kit. Configure an SoC model for the HDL code generation by using the HDL Workflow Advisor. Generate the HDL code for your algorithm, build and deploy the HDL design on an RFSoC device, and run a MATLAB^® script to interactively capture data from the deployed HDL design.

Topics

Create RFSoC HDL Coder Models
This workflow customizes and designs an RFSoC model using the Zynq RFSoC Template Builder tool.
ARM Targeting
Design and deploy algorithms to the ARM^® processor.

Tools

Zynq RFSoC Template Builder

Generate template model based on selected RFSoC reference design (Since R2021a)

Featured Examples

DAC and ADC Loopback Data Capture

Capture raw analog-to-digital converter (ADC) data using the FPGA I/O API from the Xilinx® Zynq® UltraScale+™; ZCU111 evaluation kit or Xilinx Zynq UltraScale+ ZCU216 evaluation kit. This example uses the HDL Workflow Advisor to configure an SoC model for HDL code generation. In this example, you generate the HDL code for your algorithm, build and deploy the HDL design on an RFSoC device, and run a MATLAB® script to interactively capture data from the deployed HDL design.

Open Script

IQ Mixer Mode Capture

Enable the RFSoC built-in numerically-controlled oscillator (NCO) mixer. The mixer design uses a different data format that, instead of providing real signals, provides a complex in-phase and quadrature (IQ) signal to a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC). There is more data to transfer to direct memory access (DMA) and back to MATLAB® given that you need to transfer I and Q samples back. You can accommodate this larger data width by increasing the DMA data width to 128 bits.

Open Script