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Clocking and Multirate Design

Clock generation, HDL code generation guidelines for multirate models


Generate a Global Oversampling Clock

In many designs, the DUT is not self-contained.

Code Generation from Multirate Models

Overview of HDL code generation for single-clock, single-tasking multirate models

Multirate Model Requirements for HDL Code Generation

Guidelines for setting up multirate models and blocks for HDL code generation.

Timing Controller for Multirate Models

A timing controller entity generates the required rates from a single master clock, using one or more counters to create multiple clock enables.

Generate Reset for Timing Controller

How to generate reset for timing controller.

Using Triggered Subsystems for HDL Code Generation

How to use Triggered Subsystems, Trigger As Clock property, and generate HDL code.

Featured Examples