Hardware-Software Co-Design Basics

Learn about the hardware-software co-design workflow and how to use the Workflow Advisor to run the algorithm on the SoC platform

You can use the hardware-software co-design workflow to partition your design to run on SoC platforms. By using the HDL Workflow Advisor, you can use the IP Core Generation workflow to generate an HDL IP core that runs on the FPGA on board the SoC. Using Embedded Coder^®, you can generate and build the embedded software, and run it on the ARM^® processor.

Topics

Hardware-Software Co-Design Workflow for SoC Platforms
High-level workflow steps for targeting an SoC platform.
Getting Started with the HDL Workflow Advisor
Learn the basics of the HDL Workflow Advisor and how to run various tasks.
Run HDL Workflow with a Script
Export, import, or configure an HDL Workflow CLI command script.

Featured Examples

Get Started with HDL Workflow Command-Line Interface

Use the HDL Workflow Advisor to run HDL workflows from the command line and the Export to Script option.

Open Script

Getting Started with Targeting Zynq UltraScale+ MPSoC Platform

Use the hardware-software co-design workflow to blink LEDs at various frequencies on the Xilinx® Zynq® UltraScale+ MPSoC.

Open Script

IP Core Generation of an I2C Controller IP to Configure the Audio Codec Chip

Illustrates how to model an I2C controller using an I2C Master controller modeled using Stateflow® blocks for configuring the audio codec chip.

Open Script