HDL Test Bench Generation

R2026b

Generate a test bench that verifies generated HDL code against test vectors from MATLAB^® or Simulink^®

When you generate HDL code, you can optionally generate an HDL test bench that verifies the generated HDL DUT against test vectors saved from your Simulink model or from the MATLAB code. You can also collect code coverage information from the tests run by the generated test bench. For more information on how to select and run a test bench, see Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor.

Functions

makehdltb Generate HDL test bench from model or subsystem

Model Settings

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Test Bench

Simulation tool	Simulator to use to run generated test benches
HDL code coverage	Enable HDL code coverage flags in generated simulator scripts
HDL test bench	Enable HDL test bench generation
Cosimulation model	Generate cosimulation model
SystemVerilog DPI test bench	Enable SystemVerilog DPI test bench generation
Test bench name postfix	Suffix to append to test bench name
Force clock	Whether test bench forces clock input signals
Clock high time (ns)	Period during which test bench drives clock input signals high
Clock low time (ns)	Period during which test bench drives clock input signals low
Hold time (ns)	Hold time for input signals and forced reset input signals
Force clock enable	Whether test bench forces clock enable input signals
Clock enable delay (in clock cycles)	Elapsed time between deassertion of reset and assertion of clock enable
Force reset	Whether test bench forces reset input signals
Reset length (in clock cycles)	Length of time during which reset is asserted
Hold input data between samples	Hold data values for subrate signals for number of base-rate clock cycles in subrate sample period
Initialize test bench inputs	Specify initial value driven on test bench inputs before data is asserted to DUT
Multi-file test bench	Divide generated test bench into helper functions, data, and HDL test bench code files
Test bench data file name postfix	Suffix to append to test bench data file name when generating multi-file test bench
Test bench reference postfix	Suffix to append to names of reference signals generated in test bench code
Use file I/O to read/write test bench data	Create data files for reading and writing test bench input and output data
Ignore output data checking (number of samples)	Number of samples during which output data checking is suppressed
Floating point tolerance check based on	Check for errors in floating-point library based on relative or ULP errors
Tolerance Value	Floating-point tolerance value
Simulation library path	Path of compiled Altera or AMD simulation libraries

Topics

Verification Basics

Choose a Test Bench for Generated HDL Code
Select a generated test bench.
Generated Model and Validation Model
The generated model is a model created during HDL code generation that shows the HDL implementation architecture and includes latency.

HDL Test Bench for MATLAB Code

Verify Code with HDL Test Bench
Simulate the generated HDL design under test (DUT) with test vectors from the test bench using the specified simulation tool.
Using Test Benches With HDL and HLS Code Generation
MATLAB test bench requirements and best practices for HDL and High-Level Synthesis (HLS) code generation.
Test Bench Generation
HDL Coder™ writes the DUT stimulus and reference data from your MATLAB or Simulink simulation to data files (.dat).
Specify Test Bench Clock Enable Toggle Rate
Specify test bench clock enable toggle rate.

HDL Test Bench for Simulink Model

Verify Generated HDL Code from Simulink Model
Generate an HDL test bench to verify the VHDL^® or Verilog^® Code.
Verify Generated Code Using HDL Test Bench at Command Line
Learn how to generate an HDL test bench to verify the VHDL, Verilog or SystemVerilog Code.
Test Bench Generation
Learn how HDL test bench generation works.
Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor
Generate test bench and code coverage for generated HDL code using the HDL Workflow Advisor.
Test Bench Block Restrictions
Determine which blocks do not support direct connection to the DUT for test bench generation.

Troubleshooting

Resolve Index Errors During HDL Simulation

Troubleshoot index errors during HDL code simulation.

Featured Examples

Locate Numeric Differences After Speed Optimization

Learn about numeric differences between original and generated models.

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