Model References
R2026bA model reference allows you to use a Model block to reference another model, creating a hierarchical structure. Each referenced model has a clearly defined interface that specifies the characteristics of its inputs and outputs. This interface ensures that the referenced model functions independently of its placement within the hierarchy. Model references are especially beneficial to partition a large design into a hierarchy of smaller designs for code reuse, modular development, and accelerated simulation.
Model Settings
| Generate VHDL or SystemVerilog code for model references into a single library | Generate VHDL or SystemVerilog code in separate libraries |
| Generate parameterized HDL code from masked subsystem | Generate reusable HDL code for subsystems |
| Preserve Bus structure in the generated HDL code | Generate code with VHDL record or SystemVerilog structure types (Since R2022b) |
| Code reuse | Specify whether to generate a reusable file for subsystems (Since R2022a) |
Topics
- Generate Parameterized Code for Referenced Models
Generate VHDL®
generic, Verilog® or SystemVerilogparameterfor model arguments in a model reference. - Model Referencing for HDL Code Generation
Generate HDL code for referenced models.
- Generate Incremental HDL Code for Referenced Models
When incremental code is generated for referenced models.
- Set Configuration Parameters for HDL Code Generation of Model Hierarchies
Satisfy model reference hierarchy requirements to enable HDL code generation.
- Generate Black Box Interface for Referenced Model
Specify a black box implementation for the Model block when you already have legacy or manually-written HDL code.
Featured Examples
Field-Oriented Control of a Permanent Magnet Synchronous Machine
Generate HDL code for a Field-Oriented Control (FOC) algorithm for a Permanent Magnet Synchronous Machine (PMSM).
