Model Configuration Parameters: Test Bench
The Test Bench category lets you set options that determine characteristics of generated test bench code.
These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Test Bench category.
| Parameter | Description |
|---|---|
| Simulation tool | Simulator to use to run generated test benches |
| HDL code coverage | Enable HDL code coverage flags in generated simulator scripts |
| HDL test bench | Enable HDL test bench generation |
| Cosimulation model | Generate cosimulation model |
| SystemVerilog DPI test bench | Enable SystemVerilog DPI test bench generation |
| Test bench name postfix | Suffix to append to test bench name |
| Force clock | Whether test bench forces clock input signals |
| Clock high time (ns) | Period during which test bench drives clock input signals high |
| Clock low time (ns) | Period during which test bench drives clock input signals low |
| Hold time (ns) | Hold time for input signals and forced reset input signals |
| Force clock enable | Whether test bench forces clock enable input signals |
| Clock enable delay (in clock cycles) | Elapsed time between deassertion of reset and assertion of clock enable |
| Force reset | Whether test bench forces reset input signals |
| Reset length (in clock cycles) | Length of time during which reset is asserted |
| Hold input data between samples | Hold data values for subrate signals for number of base-rate clock cycles in subrate sample period |
| Initialize test bench inputs | Specify initial value driven on test bench inputs before data is asserted to DUT |
| Multi-file test bench | Divide generated test bench into helper functions, data, and HDL test bench code files |
| Test bench data file name postfix | Suffix to append to test bench data file name when generating multi-file test bench |
| Test bench reference postfix | Suffix to append to names of reference signals generated in test bench code |
| Use file I/O to read/write test bench data | Create data files for reading and writing test bench input and output data |
| Ignore output data checking (number of samples) | Number of samples during which output data checking is suppressed |
| Floating point tolerance check based on | Check for errors in floating-point library based on relative or ULP errors |
| Tolerance Value | Floating-point tolerance value |
| Floating point tolerance check | Specify the floating-point tolerance check option |
| Tolerance Value | Enter the tolerance value based on the floating-point tolerance check setting that you specify |
| Simulation library path | Path of compiled Altera® or Xilinx® simulation libraries |
The Configuration Parameters dialog box also includes other code generation parameters:
Generate Test Bench Button
The Generate Test Bench button initiates test bench
generation for the system selected in the Generate HDL for menu
on the parent HDL Code Generation pane. Make sure that the system selected is the
DUT. Testbench generation is disabled if you select the entire model. See also
makehdltb.
