Algorithm Verification

Link MATLAB® or Simulink® to your HDL design

Create a communication link between the your HDL design and MATLAB or Simulink. Your HDL can execute in simulation or on an FPGA.

  • HDL Cosimulation enables you to run a Simulink or MATLAB simulation that is synchronized with an HDL design simulating with HDL simulators from Siemens®, Cadence®, Synopsys®, and AMD®.

  • FPGA-in-the-Loop (FIL) enables you to run a Simulink or MATLAB simulation that is synchronized with an HDL design running on an AMD, Intel®, or Microchip FPGA board.

These features enable you to:

  • Verify an HDL implementation against the model.

  • Create testbenches for HDL code.

  • Use a behavioral model as a reference in an HDL simulation.

  • Verify an HDL implementation on FPGA hardware.

  • Use analysis and visualization features to gain insight into an HDL implementation.

  • Integrate a new model with an existing HDL design.

  • Apply test scenarios from MATLAB or Simulink to the HDL design on the FPGA.

These features are not available in MATLAB Online™.

Before you can use FIL simulation, you must download the support package for your board. See Download FPGA Board Support Package.

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