To get started, see Verify HDL Module with Simulink Test Bench.
|Cosimulation Wizard||Generate a cosimulation block or System object from existing HDL files|
|Load instantiated HDL module for cosimulation with Cadence Incisive and Simulink|
|Start and configure Cadence Incisive simulators for use with HDL Verifier software|
|Start and configure ModelSim for use with HDL Verifier|
|Load instantiated HDL module for cosimulation with ModelSim and Simulink|
To cosimulate your HDL code with a MATLAB® or Simulink design, you must first:
List of supported third-party EDA software and FPGA boards.
Set up the connection between the HDL simulator and Simulink.
Provides some direction for choosing TCP/IP socket ports.
Provides instructions for performing cosimulation across a local network.
Provides an introduction to the process for integrating HDL Verifier™ blocks into a Simulink design.
The steps to code and run a Simulink-as-test bench cosimulation for use with the HDL Verifier software.
The steps for setting up an HDL Verifier session that uses Simulink to verify a simple VHDL® model.
Provides instruction in using the Cosimulation Wizard to create a Simulink model for cosimulation.
Generate test bench and code coverage for generated HDL code using the HDL Workflow Advisor.
Verify generated HDL code using a generated cosimulation model.
Provides an introduction to the process for integrating blocks into a Simulink design.
Provides a high-level view of the steps involved in coding and running a Simulink-as-component cosimulation for use with the software.
The HDL Verifier software consists of MATLAB functions, a MATLAB System object™, and a library of Simulink blocks, all of which establish communication links between the HDL simulator and MATLAB or Simulink.
Next steps after you generate a function or block representing your HDL module.
Prepare for cosimulation and choose whether to cosimulate your HDL code as a function, System object, or block.
Generate a Simulink block to cosimulate your HDL code.
Run your test bench or algorithm, including the cosimulation of your HDL module.
The representation of simulation time differs significantly between the HDL simulator and Simulink.
You can create rising-edge or falling-edge clocks, resets, or clock enable signals that apply internal stimuli to your model under cosimulation.
Provides suggestions for optimizing your cosimulation performance.
If your HDL application needs to send HDL data to a MATLAB function, you may first need to convert the data to a type supported by MATLAB and the HDL Verifier software.
Describes ways to avoid race conditions in hardware cosimulations with MATLAB and Simulink software.
A value change dump (VCD) file logs changes to variable values, such as the values of signals, in a file during a simulation session.
Guides you through the basic steps for adding a To VCD File block to a Simulink model for use with cosimulation.