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Configure comparison for each signal value

Since R2022a



setCaptureCondition(DC,name,enable,value) configures a capture value comparison for the signal name. DC is a customized data capture object. The enable argument indicates whether this signal is part of the overall capture condition.


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This example uses a customized data capture object, DC, that defines two signals for both trigger and data capture. Signal A is 1 bit and signal B is 8 bits.

Enable capture condition logic.

DC.EnableCaptureCtrl = true;

To enable capture condition logic, you must select the Include capture condition logic parameter while generating the data capture IP core using the FPGA Data Capture Component Generator tool.

Set up a capture condition to capture data when the FPGA detects a high value on signal A and a value 17 on signal B.


Input Arguments

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Customized data capture object, specified as an hdlverifier.FPGADataReader System object.

Name of the capture component signal, specified as a character vector.

This name must match one of the signal names configured on creation of the input System object DC. The signal must be configured as a possible trigger signal.

Data Types: char

Indication that the signal is part of the capture condition, specified as true or false. To use this signal in the overall capture condition, set this value to true. When you set this value to false, the signal is not used for the overall capture condition.

Value to compare the signal to as part of the capture condition, specified as one of the following.

  • Decimal, binary, or hexadecimal value — For a multibit signal, specify a value within the range of the data type associated with the signal. If you specify a binary or hexadecimal value, you can use an X or x to indicate signals for the function to ignore during the value comparison.

    To separate a group of bits for better readability, you can use _ between bits. For example, you can represent a 32-bit binary value as '0b1010_XXXX_1011_XXXX_1110_XXXX_1111XXXX' and a 32-bit hexadecimal value as '0xAB_CDEXFX'.

  • 'Low', 'High', 'Rising edge', 'Falling edge', or 'Both edges' — For a logical signal, specify a string that indicates the level or edge to match. For more information, see Capture Conditions.

Version History

Introduced in R2022a