Detect and Address Bugs
Simulink® Design Verifier™ uses formal methods to identify hard-to-find design errors in models without requiring extensive tests or simulation runs. Design errors detected include runtime errors such as integer overflow, division by zero, and violations of design assertions and logical errors that indicate operating conditions that cannot occur. You use Simulink Design Verifier to highlight blocks in a model containing design errors and blocks proven to be without them. For each block with an error, you calculate signal-range boundaries and generate a test vector that reproduces the error in simulation.
Design Error Detection Basics
- What Is Design Error Detection?
- Analyze Models for Design Errors
- Analyze Models for Standards Compliance and Design Errors
- Derived Ranges in Design Error Detection
- Model Advisor Checks for Analysis
- Check for Specified Minimum and Maximum Value Violations
- Perform Functional Testing and Analyze Test Coverage
Categories
- Detect and Address Run-Time Errors
Detect design errors, generate counterexamples
- Detect and Address Logical Errors
Identify logical errors in your model by using dead logic detection
Featured Examples
Detect Integer Overflow Errors
Detect integer overflow errors in a model by using design error detection analysis. Simulink® Design Verifier™ identifies the model constructs that may result in integer overflows and then either proves that the integer overflow cannot occur during simulation or generates test cases that demonstrates the integer overflow error.
Detect Out of Bound Array Access Example Model
Detect out of bound array access errors in a model.
Analyze Results for Dead Logic Analysis
Determine potential causes for dead logic in the analysis.
