Simulink Design Verifier
Simulink® Design Verifier™ uses formal methods to identify hidden design errors in models. It detects blocks in the model that result in integer overflow, dead logic, array access violations, and division by zero. It can formally verify that the design meets functional requirements. For each design error or requirements violation, it generates a simulation test case for debugging.
Simulink Design Verifier generates test cases for model coverage and custom objectives to extend existing requirements-based test cases. These test cases drive your model to satisfy condition, decision, modified condition/decision (MCDC), and custom coverage objectives. In addition to coverage objectives, you can specify custom test objectives to automatically generate requirements-based test cases.
Learn the basics of Simulink Design Verifier
Identify analyzable components for unit or system-level testing, address model incompatibilities or analysis timeout
Detect run-time errors and logical errors, debug issues in your design
Verify design against requirements, refine counterexamples by using input assumptions
Generate sets of tests to satisfy model and code coverage and custom testing criteria
Test behavioral equivalence of model and generated code, or models run in different Simulink releases
Log and review analysis results, generate report, inspect test cases
Qualify Simulink Design Verifier for IEC Certification