CCSDS LDPC Decoder
Libraries:
Wireless HDL Toolbox /
Error Detection and Correction
Description
The CCSDS LPDC Decoder block implements a lowdensity paritycheck (LDPC) decoder using a layered belief propagation algorithm with minsum approximation for decoding LDPC codes according to the Consultative Committee for Space Data Systems (CCSDS) standard [1]. The block accepts loglikelihood ratio (LLR) values, a stream of control signals, a block length, and a code rate as inputs. The block outputs decoded bits, a stream of control signals, and a signal that indicates when the block is ready to accept new inputs.
The block supports scalar inputs and vector inputs of size 8. The block supports early termination to improve decoding performance and convergence speeds at high signaltonoise ratio (SNR) conditions.
The block provides an architecture suitable for HDL code generation and hardware deployment. You can use this block in a CCSDS receiver for satellite communication.
Examples
Ports
Input
data — LLR values
scalar  eightelement row vector
LLR values, specified as a scalar or an eightelement row vector.
For HDL code generation, specify this value in signed fixedpoint format. The input word length must be an integer in the range [4, 16] and the fractional length must be in the range [0, 15].
Data Types: int8
 int16
 signed fixed point
ctrl — Control signals accompanying sample stream
samplecontrol
bus
Control signals accompanying the sample stream, specified as a
samplecontrol
bus. The bus includes the start
,
end
, and valid
control signals, which indicate the
boundaries of the frame and the validity of the samples.
start
— Indicates the start of the input frameend
— Indicates the end of the input framevalid
— Indicates that the data on the input data port is valid
For more details, see Sample Control Bus.
Data Types: bus
codeRateIdx — Code rate index
0
 1
 2
Code rate index, specified as 0
, 1
, or
2
. You must specify this value in the
fixdt(0,2,0)
format. Each code rate index value represents a
specific code rate, as this table shows.
codeRateIdx Value  Code Rate 

0
 1/2 
1  2/3 
2  4/5 
Dependencies
To enable this port, set the Configuration type parameter
to AR4JA LDPC
.
Data Types: fixdt(0,2,0)
blkLenIdx — Block length index
0
 1
 2
Block length index, specified as 0
, 1
, or
2
. You must specify this value in the
fixdt(0,2,0)
format.
The block length varies with the specified block length index. The input block length must be a multiple of 8. This table shows the block length index values and their corresponding block lengths.
blkLenIdx Value  Block Length 

0
 1024 
1  4096 
2  16384 
Dependencies
To enable this port, set the Configuration type parameter
to AR4JA LDPC
.
Data Types: fixdt(0,2,0)
iter — Number of iterations
integer in the range [1, 63]
Number of iterations, specified as an unsigned integer in the range [1, 63].
If you specify an iter value greater than 63 or less than 1,
the block overrides your specification and sets the iter value to
8
before it performs decoding.
Dependencies
To enable this port, set the Decoding termination criteria
parameter to Max
and the Source for number of
iterations parameter to Input port
.
Data Types: uint8
Output
data — Decoded bits
scalar  eightelement row vector
Decoded bits, returned as a Boolean scalar or an eightelement row vector of Boolean values.
Data Types: Boolean
ctrl — Control signals accompanying sample stream
samplecontrol
bus
Control signals accompanying the sample stream, returned as a samplecontrol
bus. The bus includes the start
, end
, and
valid
control signals, which indicate the boundaries of the frame
and the validity of the samples.
start
— Indicates the start of the output frameend
— Indicates the end of the output framevalid
— Indicates that the data on the output data port is valid
For more details, see Sample Control Bus.
Data Types: bus
nextFrame — Block ready indicator
0
 1
Block ready indicator, returned as a Boolean scalar.
The block sets this signal to 1
when the block is ready to
accept the start of the next frame. If the block receives an input
ctrl.start signal while nextFrame is
0
, the block discards the frame in progress and begins processing
the new data.
Data Types: Boolean
actIter — Actual number of iterations
positive scalar
Actual number of iterations the block takes to decode the output, returned as a positive scalar.
Dependencies
To enable this port, set the Decoding termination criteria
parameter to Early
.
Data Types: uint8
parityCheck — Parity check status indicator
0
 1
Parity check status indicator, returned as a Boolean scalar. The port indicates the status of the parity check after the decoding operation.
0
— Indicates that the parity check failed1
— Indicates that the parity check passed
Dependencies
To enable this port, select the Enable parity check output port parameter.
Data Types: Boolean
Parameters
Configuration type — Type of configuration
(8160,7136) LDPC
(default) 
AR4JA LDPC
Select the configuration type. For more information about the supported configurations, see [1].
Decoding termination criteria — Termination criteria
Max
(default) 
Early
Select the decoding termination criteria.
Max
— Terminate decoding when the block reaches the number of iterations specified in the block mask or the iter input port.Early
— Terminate decoding when the block completes all of the parity checks or when the block reaches the maximum number of iterations specified in the block mask.
Source for number of iterations — Source selection for number of iterations
Property
(default)  Input port
Select the source for specifying the number of iterations.
You can set the number of iterations by using an input port or a parameter.
Property
— Select this option to enable the Number of iterations parameter.Input port
— Select this option to enable the iter port.
Number of iterations — Number of decoding iterations
8
(default)  integer in the range [1, 63]
Specify the number of decoding iterations.
Dependencies
To enable this parameter, set the Decoding termination
criteria parameter to Max
and the
Source for number of iterations parameter to
Property
.
Maximum number of iterations — Maximum number of decoding iterations
8
(default)  integer in the range [1, 63]
Specify the maximum number of decoding iterations.
Dependencies
To enable this parameter, set the Decoding termination
criteria parameter to Early
and set the
Source for number of iterations parameter to
Property
.
Enable parity check output port — Parity check status
off
(default)  on
Select this parameter to enable the parityCheck output port. Use this output port to view the status of the parity check.
Algorithms
This figure shows the architecture block diagram of the CCSDS LDPC Decoder block. The Controller block controls the layer and iteration count of the decoding process. The Variable node RAM block stores the variable node (VN) messages, and the Check node RAM block stores the check node (CN) messages. The Functional Unit block calculates the VN messages and CN messages based on the layered belief propagation and either the normalized minsum approximation algorithm or the minsum approximation algorithm. The Termination/Parity check status block calculates the parity checks and provides the parity check status after each iteration. For more information about the decoding algorithms, see the following sections.
Belief Propagation Decoding
The implementation of the belief propagation algorithm is based on the decoding algorithm presented in [4]. For a transmitted LDPCencoded codeword c, where $$c=({c}_{0},{c}_{1},\mathrm{...},{c}_{n1})$$, the input to the LDPC decoder is the loglikelihood ratio (LLR) value $$L({c}_{i})=\mathrm{log}\left(\frac{\mathrm{Pr}({c}_{i}=0\text{channeloutputfor}{c}_{i})}{\mathrm{Pr}({c}_{i}=1\text{channeloutputfor}{c}_{i})}\right)$$.
In each iteration, the key components of the algorithm are updated based on these equations:
$$L({r}_{ji})=2\text{\hspace{0.17em}}\text{atanh}\text{\hspace{0.17em}}\left({\displaystyle \prod _{{i}^{\prime}\in {V}_{j}\backslash i}\mathrm{tanh}\left(\frac{1}{2}L({q}_{{i}^{\prime}j})\right)}\right)$$,
$$L({q}_{ij})=L({c}_{i})+{\displaystyle \sum _{{j}^{\prime}\in {C}_{i}\backslash j}L({r}_{{j}^{\prime}i})}$$, initialized as $$L({q}_{ij})=L({c}_{i})$$ before the first iteration, and
$$L({Q}_{i})=L({c}_{i})+{\displaystyle \sum _{{j}^{\prime}\in {C}_{i}}L({r}_{{j}^{\prime}i})}$$.
At the end of each iteration, $$L({Q}_{i})$$ is an updated estimate of the LLR value for the transmitted bit $${c}_{i}$$. The value $$L({Q}_{i})$$ is the softdecision output for $${c}_{i}$$. If $$L({Q}_{i})<0$$, the harddecision output for $${c}_{i}$$ is 1. Otherwise, the output is 0.
Layered Belief Propagation Decoding
The implementation of the layered belief propagation algorithm is based on the decoding algorithm presented in [5], section II.A. The decoding loop iterates over subsets of rows (layers) of the paritycheck matrix (PCM). For each row m, in a layer and each bit index j, the implementation updates the key components of the algorithm based on these equations:
(1) $$L({q}_{mj})=L({q}_{j}){R}_{mj}$$,
(2) $${A}_{mj}={\displaystyle \sum _{\begin{array}{c}n\in N\left(m\right)\\ n\ne j\end{array}}\text{\psi}(L({q}_{mn}))}$$,
(3) $${s}_{mj}={\displaystyle \prod _{\begin{array}{c}n\in N\left(m\right)\\ n\ne j\end{array}}\text{sign}(L({q}_{mn}))}$$,
(4) $${R}_{mj}={s}_{mj}\text{\psi}({A}_{mj})$$, and
(5) $$L({q}_{j})=L({q}_{mj})+{R}_{mj}$$.
For each layer, the decoding equation (5) works on the combined input obtained from the current LLR inputs $$L({q}_{mj})$$ and the previous layer updates $${R}_{mj}$$.
Because only a subset of the nodes is updated in a layer, the layered belief propagation algorithm is faster than the belief propagation algorithm. To achieve the same error rate as attained with belief propagation decoding, use half the number of decoding iterations when using the layered belief propagation algorithm.
MinSum Approximation
The implementation of the minsum approximation algorithm follows the layered belief propagation algorithm with equation (2) replaced by
$${A}_{mj}=\underset{\begin{array}{c}n\in N\left(m\right)\\ n\ne j\end{array}}{\mathrm{min}}(\leftL({q}_{mn})\right\cdot \alpha )$$,
where α is 1.
Latency
The latency of the block varies based on the selected Configuration type parameter value, the values of the blkLenIdx and codeRateIdx input ports, and the number of iterations. Because the latency varies, use the nextFrame control signal output port to determine when the block is ready for a new input frame.
The latency of the block is equal to rt + d + L. In this calculation, r is the number of iterations, t is the number of clocks required to decode one iteration, d is the pipeline delay, and L is the length of the input data.
Configuration Type  Code Rate  Block Length  Number Of Clocks Per Iteration  Pipleline Delay (d) 

(8160,7136) LDPC  7/8  8160  2080  27 for scalar and 26 for vector 
AR4JA LDPC  1/2  2048  252  10 
8192  1240  
32768  4960  
2/3  1536  316  
6144  844  
24576  3376  
4/5  1280  444  
5120  482  
204800  2584 
This figure shows a sample output and latency of the CCSDS LDPC Decoder
block for a vector input when you set the Configuration type parameter
to AR4JA LDPC
, the Decoding termination criteria
parameter to Max
, the Number of iterations parameter
to 8
, and the codeRateIdx input port value to
0
. The latency of the block is 2281 clock cycles.
EbNo and BER Plots
This section shows the EbNo and BER plots of the block for specified inputs and parameter settings.
This plot shows the performance of the block for a 4 bit BPSK modulated LLR input when
you set the Configuration type parameter to (8160,7136)
LDPC
.
This plot shows the performance of the block for a 4 bit BPSK modulated LLR input for a
block length of 1024 with code rates of 1/2, 2/3, and 4/5, respectively, when you set the
Configuration type parameter to AR4JA
LDPC
.
This plot shows the performance of the block for a 4 bit BPSK modulated LLR input for a
block length of 4096 with code rates of 1/2, 2/3, and 4/5, respectively, when you set the
Configuration type parameter to AR4JA
LDPC
.
This plot shows the performance of the block for a 4 bit BPSK modulated LLR input for a
block length of 16384 with code rates of 1/2, 2/3, and 4/5, respectively, when you set the
Configuration type parameter to AR4JA
LDPC
.
Performance
The performance of the synthesized HDL code varies with the target and synthesis options. The performance also varies based on the type of algorithm, decoding termination criteria, and the word length of the input LLR values.
This table shows the resource and performance data synthesis results of the block for
the supported CCSDS standards when you set the Configuration type
parameter to (8160,7136) LDPC
or AR4JA
LDPC
, the Number of iterations parameter to
8
, and the input LLR values as a value with the
fixdt(1,4,0)
. The generated HDL targets to the Xilinx^{®}
Zynq^{®}Ultrascale+™ MPSoC  ZCU102 Evaluation Board.
Configuration Type  Input Type  Slice LUTs  Slice Registers  Block RAMs  Maximum Frequency in MHz 

(8160,7136) LDPC  Scalar  20201  14749  96  377.1 
Vector  20580  15146  96  372.4  
AR4JA LDPC  Scalar  29753  19786  192  291.9 
Vector  28812  19854  192  287.9 
This block has similar implementation for scalar and vector inputs. So, you do not find substantial difference in the resource utilization and latency.
References
[1] TM Synchronization and Channel Coding. Recommendation for Space Data System Standards. CCSDS 131.0B3. Blue Book. Issue 3. Washington, D.C.: CCSDS, September 2017.
[2] TM Synchronization and Channel Coding. Summary of Concept and Rationale CCSDS 130.1G3. Green Book. Issue 3, June 2020.
[3] Stephen B. Wicker. Error Control Systems for Digital Communication and Storage. Prentice Hall, 1995.
[4] Gallager, R. “LowDensity ParityCheck Codes.” IEEE Transactions on Information Theory 8, no. 1 (January 1962): 21–28. https://doi.org/10.1109/TIT.1962.1057683.
[5] Hocevar, D.E. “A Reduced Complexity Decoder Architecture via Layered Decoding of LDPC Codes.” In IEEE Workshop OnSignal Processing Systems, 2004. SIPS 2004., 107–12. Austin, Texas, USA: IEEE, 2004. https://doi.org/10.1109/SIPS.2004.1363033.
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
This block supports C/C++ code generation for Simulink^{®} accelerator and rapid accelerator modes and for DPI component generation.
HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has one default HDL architecture.
ConstrainedOutputPipeline  Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is

InputPipeline  Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

OutputPipeline  Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

You cannot generate HDL for this block inside a Resettable Synchronous Subsystem (HDL Coder).
Version History
Introduced in R2022b
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