Coder error: Found unsupported matrix type at output port: 0

Hi,

We were trying to generate Verilog code from the attached matlab files. We got the following error:

   Found unsupported matrix type at output port: 0.

Kindly help us!

The error snapshot can also be found in the attachment.

Answer 1

[Tim McBrayer]

The two outputs of haar12.m are 8x128 arrays of doubles. These are matrices, and are not supported for HDL code generation. (The error message could be more helpful.) HDL Coder can support vectors (1xN or Nx1 matrices) or scalars (1x1 matrix).

In addition, think of the interface to your function as the interface to a FPGA. You have just requested an output interface of 2*8*128, or 2048, doubles. There are two issues here. First, doubles are typically not supported by 3rd party synthesis tools. If you are going to put this into actual hardware, you need to convert to fixed point or integer data.

The second issue is that you have over 2000 ports. Even if each output was only 1 bit, this is over 2000 physical pins on your package. If you use 64 bits to represent each data element, you've just designed a chip that needs 131072 pins just to handle the output, never mind the input. Needless to say such a chip does not exist.

[Jairaj]

The outputs are supposed to be sent to a different block on the same chip. And we were looking to input data from memory and output the result to a memory block. We tried to use (1xN) vector, but it returned an error indicating the size to be too large. So we tried using matrices. Isn't it possible to define memory blocks in matlab code so that it can be synthesized? Kindly give some document references (if any).

[Tim McBrayer]

There is no difficulty in generating memory blocks in MATLAB code; the size you are looking at (128kbits) is reasonable. The problem lies in your attempt to transfer this entire RAM contents in one cycle from point A to point B.

Even if it's not on the primary IO pins, 128k signals (== 128k separately routed signals in the FPGA) is excessive. RAMs an an FPGA typically have only one or two ports to read/write from/to in a single clock cycle. These ports can each easily be an arbitrary width. The point is that you have to design around word access, scheduling your RAM accesses to fetch a particular word at a particular time, not wholesale full-ram copies. You will need to develop streaming interfaces both inside your chip and at the interface to handle such amounts of data.

There are several clearly labeled examples provided with HDL Coder that show modeling RAMs and ROMs. One such example is titled "Implement RAM Using MATLAB Code". Its MATLAB-internal link is web(fullfile(docroot, 'hdlcoder/ug/implement-ram-using-matlab-code.html')) .