Getting Started with Targeting Xilinx Zynq Platform

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janny ring
janny ring on 3 Jan 2022
Answered: Steve Kuznicki on 25 Apr 2022
Hi,
I get the following error at : 3. Generate the IP Core.
Task "Vivado IP Packager" unsuccessful. See log for details.
Generated logfile:
****** Vivado v2021.2 (64-bit)
**** SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
**** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source vivado_ip_package.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/fangzhen/hdl_prj_3/ipcore'.
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'd:/fangzhen/hdl_prj_3/ipcore' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'd:/fangzhen/hdl_prj_3/ipcore/Subsystem_ip_v1_0/prj_ip'.)
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2021.2/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite_ARESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'IPCORE_RESETN' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'AXI4_Lite_ACLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'IPCORE_CLK' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ARESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'IPCORE_RESETN': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ACLK': Added interface parameter 'ASSOCIATED_BUSIF' with value 'AXI4_Lite'.
INFO: [IP_Flow 19-4728] Bus Interface 'AXI4_Lite_ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'AXI4_Lite_ARESETN'.
INFO: [IP_Flow 19-4728] Bus Interface 'IPCORE_CLK': Added interface parameter 'ASSOCIATED_RESET' with value 'IPCORE_RESETN'.
WARNING: [IP_Flow 19-5661] Bus Interface 'IPCORE_CLK' does not have any bus interfaces associated with it.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
ERROR: '2201031314' is an invalid argument. Please specify an integer value.
while executing
"rdi::set_property core_revision 2201031314 {component component_1}"
invoked from within
"set_property core_revision 2201031314 [ipx::current_core]"
(file "vivado_ip_package.tcl" line 32)
INFO: [Common 17-206] Exiting Vivado at Mon Jan 3 13:15:01 2022...
Elapsed time is 11.5705 seconds.
I have tried re-download vivado ,thingds did't turn better.
I am using Vivado 2020.2.
Accordingly, I set up the Xilinx Vivado synthesis tool path using the following command:
hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'D:\Xilinx2\Vivado\2020.2\bin\vivado.bat');
Upon typing h = zynq in the command window I get:
h = zynq
h =
LinuxShell with properties:
IPAddress: '169.254.0.2'
Username: 'root'
Port: 22
Any help is much appreciated!
Thanks
  5 Comments
janny ring
janny ring on 5 Jan 2022
thanks a lot. When i changed the system date ,things turn over. Thanks everyone

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Accepted Answer

kiyoko
kiyoko on 5 Jan 2022
This issue is related to a year date bug in Xilinx Vivado.
https://support.xilinx.com/s/question/0D52E00006uxy49SAA/vivado-fails-to-export-ips-with-the-error-message-bad-lexical-cast-source-type-value-could-not-be-interpreted-as-target?language=en_US

More Answers (1)

Steve Kuznicki
Steve Kuznicki on 25 Apr 2022
This is a documented bug from Xilinx for anyone trying to work with Vivado in the year 2022.
We have now released an official patch to resolve this issue for customers. Please refer to the following External Bug Report (EBR):
We have also updated the following MATLAB Answers post documenting this new solution:
This has to do with the year 2022 and the way Xilinx is creating their IP Core ID (based on int32).You should use the first (EBR) link and download the zip file. There are folders in there for several releases. You just need to replace the IPEmitterVivado.p file for your release. It's good practice to rename the original file first.

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