Simulink automatically generates Verilog. How should it run on FPGA

I have generated Verolig from part of the module, how do I run this part of Verilog on the FPGA?

“bufen”This subsystem has generated Verilog.And need to measure the time used to run on FPGA.

I plan to run the original algorithm on MATLAB and only this small part on FPGA.