How to instance datacapture module into my HDL Code?

1. I ran generateFPGADATACaptureIP in command window.

2. In Data Capture Component Generation, I put the following settings.

Ports : clk_check, led0, led1, led2, ,,, led7

(Target)

Generated IP name : datacapture

FPGA vendor : Xilinx

Generated IP language : Verilog

Connection type : JTAG

Destination folder : hdlsrc

(Capture)

Sample depth : 1024

Max trigger stages : 1

3. I connected the generated datacapture module with my original module in block deisgn using vivado's Tcl console.

4. As follows, clk is connected through the clocking wizard, and clk_enable is connected to the constant value 1. And the rest of the led port was originally connected to the port of my blinky_zcu106 module. Afterwards, validate design was executed and completed without any problems.

5. After making the generated design into hdl wrapper, the following error message occurred when bitstream was created. The error message is as follows.

[Place 30-494] The design is empty

Resolution: Check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports.

[Common 17-69] Command failed: Placer could not place all instances

How do I solve this?

Answer 1

[UDAYA PEDDIRAJU]

Hello Dongyun,

As per my understanding, the issue you’re facing is with the top-level module, it seems like you’ve followed the correct steps to integrate the data capture module into your HDL code. The error occurred because your design might be empty or that not all top-level ports have been instantiated and connected.

You can follow the below steps to resolve the issue:

1. Make sure that your design is not empty and that it contains all necessary components and modules from top level to bottom level.
2. Ensure that you have instantiated and connected all the top-level ports both in block design and in the constraint file.

I hope this helps!