How does PC build connection with UDP AXI MANAGER?

Hi,

I want to use udp axi manager to accelerate the data transmission between my pc and FPGA. However, my FPGA does not have GMII or MII ethernet port and only supports RGMII. What's worse, the Xilinx IP Core GMII_to_RGMII does not support my device. Thus, I have to use the third-party Ethernet Stack.

I have following questions.

1.How does PC communicate with the UDP AXI MANAGER? or How does PC builds connection with UDP AXI MANAGER?

2.When UDP AXI MANAGER sends data to PC, what's the destination port number of PC?

Thanks for your kindly help,

Looking forward to your reply!

Answer 1

[KH]

Hi,

This problem has been solved. I found an ip core that can convert gmii to rgmii interface.

URL: FPGA以太网篇之GMII转RGMII - Galois_V - 博客园

This ip core supports Ultrascale+ FPGA (exclude Zynq Ultrascale+), I do not know if it supports other FPGA familys.

Another question is that the ip core symbol:

Ethernet_hub_gmii_0's input port: ref_reset looks it should be active low, However, it's active high.