How can I intentionally trigger a convergence error in a Simulink model?

I have a Simulink model and I am trying to intentionally reproduce a solver convergence error for testing purposes. However, the model continues to converge successfully.

My current solver settings are:

• Fixed-step solver
• Sample time: 10 ms (0.01 s)
• Relative/absolute tolerance: 1e-12
• Maximum nonlinear iterations: 1

Given these already strict settings, what changes would increase the likelihood of generating a convergence failure?

For example:

• Should I further restrict the nonlinear solver settings?
• Would increasing the sample time make convergence more difficult?
• Are discontinuities, algebraic loops, or strong nonlinearities effective ways to trigger convergence issues?
• Could poor initial conditions or inconsistent state initialization help reproduce the problem?
• Are there specific Simulink blocks or model configurations that are known to cause convergence failures?

My goal is to understand which conditions typically lead Simulink solvers to report convergence errors and how to reproduce such errors in a controlled and repeatable manner for validation testing.

Thank you.

Answer 1

[dpb]

The clean way would be through the <Simulink Fault Analyzer>. <Simulink Design Verifier> can do verification of model for faults. Both are additional toolboxes that will need license for if don't already have, though.