It sounds like you are trying to model existing handwritten VHDL that uses generics in its interface, in Simulink, and using a System Object. And, the HDL Coder implementation of System Objects don't support generics.
One thing you could try is to wrap the System Object block inside a subsystem. This may help in one of two ways depending on your circumstances. If you are trying to black-box your existing VHDL code into a larger Simulink design, you can set the HDL Architecture of the Subsystem to a black box and connect the generics up through that interface. Alternatively, you can investigate using a masked subsystem and setting 'mask parameters as generics' in HDL Coder.