Generate Valid In, Valid Out with HDL Coder - Best practice?

I am using Matlab HDL Coder to generate VHDL Code and want to add a "valid in/out" Port to my subsystems to ensure the timing in sequential operations on a macro level.

Valid in: Triggers the calculation of the subsystem with the current values of the subsytem input ports

Valid out: Signals (e.g. with an rising edge) that the calculation of the subsystem is finished

I have tinkered with several idears:

- Enabled subsystem with a state machine outside of the subsystem to control if the output values have changed

- A parallel path inside the subsystem which just routes the valid in directly to valid out - a rising edge is sourced when the calculation is started -> with "balenced delays" the valid out signal (should) rise when the calculation is ready

- some minor variations of the above / unsucessful approches

So , what is best practice when implementing a valid in / out control for a HDL Subsytem?

Answer 1

[Ludo Visser]

I typically follow your second suggestion. I used enabled subsystems to split up the computations into blocks that can either be done in a single clock cycle (like addition, logic, etc.) or that require a predictable number of pipeline registers (e.g. multiplication). In this way, I can manage the results of the delay balancing feature (which I really dislike, but that's another discussion).

A typical subsystem looks like this:

You can see the "input valid" to "output valid" line in the top and the data line directly below it.

As you can see, I'm generous with unit delays, so I can predict better where the delay balancing will insert delays. In later stages, if I run into performance issues, I can optimize a bunch of them away, but typically it's not necessary in my applications.

[TS]

thanks for your contribution to the discussion. I pretty much kept using the second variation, which works fine for me atm.

I almost always disable balance delay on the "top level" subsystem which i generate and only use it in the underlying subsystems and "shedule" the tasks inside of the "top level" myself with enabled subsystems and an "auto-balanced-delay data line" so i know what goes on

[Ludo Visser]

I also turn it off at the top level. It's annoying that HDLWA pushes this setting so hard - it generates an error if you turn it off, which you can only bypass by setting "ignore warnings", and who knows what other warnings go unseen because of that.