Simulink Design Verifier is not creating test cases.

Hi, I am having this issue where the Simulink Design Verifier is not creating the test harness and insisting that I did not give any test cases for it to work.

This is the error that I encountered:

The analysis did not produce a harness model. Data does not contain any test cases or counterexamples.

I tried using the matlab command window and Design Verifier to do it and it still give that same result where no test harness is created.

[Pat Canny]

Which SLDV functions are you using from the MATLAB Command Window? I assume "sldvmakeharness", is that correct? If so, which input arguments are you including in the function call?

[Meiying Goh]

sldvmakeharness("the model that I am running")

Answer 1

[Ankita Bansal]

Hi, what are the set of commands/steps you are using to create the harness model.

sldvmakeharness('model name') creates empty harness model. If you want to create test harness, then you need to give testcases also as input and you can generate testcases using 'sldvrun'. After that you can use model name and generated test cases ( datafile ) as parameters in sldvmakeharness('model name' , 'datafile').

Hope this helps

[Meiying Goh]

My initial plan was to create a set of test cases from the model. So, I tried creating a set of test cases by using the generate test function in matlab. But, it does not analysis the objectives almost immediately.

Please refer to the image that I had attached.

Hence, I went to research on possible way to generate test cases and I followed one of mathwork example. The steps were to create my own test cases, generate a harness model, import the test cases into the signal builder, run it, save the cvt file and run the cvt file with the model and it also produce the same result as the image.

This is the link that I refer to: https://www.youtube.com/watch?v=33EiOfCRpSQ&t=1581s

Moreover, I tried to use the example that is provided by mathlab, such as sldvdemo_flipflop and it still doesn't produce any test cases.

Please do look into this. Thank you very much.

Answer 2

[Bill Aldrich]

Based on the screenshot of your status window, I see that all of the test objectives have are undecided after just 1 second of analysis. This indicates some unexpected issue in the analysis. For example, you might have min/max settings on a signal specified as -1..1 and then feed the signal a value outside that range, say 5. This behavior could also indicate a bug within the tool or a problem with your installation.

I suggest you contact MathWorks support and provide a copy of the log file of the analysis and any other details you have so we can better help you. We need to know some details about the product version and the machine you are using.

The sldvmakeharness command is expected to produce the error you are seeing because you have 0 objectives satisfied by test cases.