wrong frequency of F280049 ePWM Texas Instruments

Hello,

I just implement a simple ePWM model.

I checked the frequency on my oscilloscope, but there is a difference of factor 10.

The CPU frequency is 100MHz and I would like to generate an 500kHz PWM, but I get a frequency of 50kHz.

I implement the same behaviour with the timer period inside of the ePWM block.

There is also a difference of factor 10.

I attached my file. Thanks for your help.

[Sander Rots]

I have the same problem.

Using 280049 MCU on a custom board, using the internal MCU oscillator.

I also get PWM signals with a frequency that is a factor 10 lower than I expect.

The same thing happens when I toggle a GPIO, here the toggling frequency is also a factor 10 lower than expected.

Does anybody know what the cause of this problem is?

Answer 1

[Sander Rots]

I think I found the cause of the issue. The “auto set PLL based on OSCCLK and CPU clock” under “Clocking” in the “Target hardware options” is set to a unsafe value of 100Mhz (when the internal oscillator is used).

In the SPRUI33D document for the 28004x microcontroller, chapter 3.7.9 (Choosing PLL Settings), states that: f_PLLSYSCLK = f_OSCCLK*(SYSPLLMULT.IMULT + SYSPLLMULT.FMULT)/(SYSPLLMULT.ODIV*SYSCLKDIVSEL.PLLSYSCLKDIV), where f_OSCCLK is the system oscillator frequency, which is 10MHz+-3% when using the internal oscillator. The note at the end of 3.7.9 states that: “The system clock frequency (PLLSYSCLK) may not exceed the limits specified in the data sheet’s f(SYSCLK) parameter. These limits do not allow for oscillator tolerance”.

The standard “auto set PLL based on OSCCLK and CPU clock” PLL settings under the “Target hardware options” in Matlab do not take this note into account. It generates a PLLSYSCLK of 100MHz when OSCCLK is 10MHz. This is within the limits, but when OSCCLK is at its maximum limit/deviation of +3% this setting would give a PLLSYSCLK of 103MHz, exceeding the limit that was discussed in the note.

SPRUI33D chapter 3.7.11 shows an example for generating a CPU frequency of 100MHz (well kind of 100MHz, close to it at least). Here they use IMULT = 19, FMULT = 0.25, ODIV =1, PLLSYSCLKDIV = 2. These setting generate a PLLSYSCLK of 96.25MHz when OSCCLK is 10MHz. When OSCCLK is 10.3MHz the resulting PLLSYSCLK will be 99.14MHz, staying within the limit of 100MHz for the CPU frequency.

If we now apply these PLL settings under “Target hardware options” in Matlab we would get: SYSPLLMULT = 19.25, ODIV = 1, SYSDIVSEL = 2. If you now “build, deploy and start” with these settings the CPU clock frequency will be much closer to the desired 100MHz, instead of the 10MHz that the standard (faulty) settings gives. These settings will never give a CPU frequency of exactly 100MHz, but this is due to the relatively large oscillator tolerance of the internal crystal. So if you want a CPU frequency that is closer to 100MHz you will have to use an external oscillator that has a lower frequency tolerance.

The following forum topic also discusses this problem (however not specifically for Matlab embedded coder): https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/853295/tms320f280049-how-to-config-f280049-run-at-100mhz-with-internal-oscilator