Using Simulink FPGA-in-the-loop (FIL) with USB3 cam and ZCU104?

We have planned a "project A" where we suppose a video stream from the real USB3 camera (See3CAM from e-con) on the Zynq+ board ZCU104 is feed into Computer Vision / Detection Algorithms embedded in the Zynq+ SoC, producing resulting HDMI output out of the ZCU104 board (monitored on a HDMI video monitor) and producing results/extracted parameters fed back to the connected Simulink program for further processing by the HS3 JTAG bus.

The XILINX Zynq+ board is the ZCU104 using Diligent HS3 JTAG. We have been happy to already have received an unofficial board definition file (ZCU104-HS3.xml) from Eduard Benet in the

MathWorks Technical Support Department (Technical Support Case #03657533).

We have already seen that we can run a simpler FIL example (fir_pid) on the ZCU104, based on the received board definition file. we used the Vivado 2018.3.

How can we proceed to be able to establish the "project A" as described? For example, do you have a base Simulink CV design we can develop further which has this real video input/output connectivities?

Answer 1

[Charan Jadigam]

Hi,

ZCU104 has been brought into support in R2019b version and you can check in our release-notes.

Unfortunately, we currently have no support for USB cameras.

Hope this helps!