I am trying to generate HDL code for a Xilix FPGA board using the HDL coder. I cannot say I understand the whole process in depth, but it has 5 stages that need to be executed in order and take care of the model built, the peripherals used on the board, the FPGA arrangement and so on. I consistently get the same error at the mapping stage, error log attached to the thread. The error follows me through models, even a simple unit delat with input and output, so I dare say it is not model-dependent.
From what Im gathering it has to do with a license error of either my Xilinx or my Windows. Has anyone encountered a simmilar error before, does anyone have solutions that work?