Sequential logic or combinational logic

Dear all,

I have met a problem. It is that timing constraint is not satisfied when my design runs under a very high clock frequency. The problem must be result from combinational logic circuit which is generated by HDL coder.

Here is my question: Can hdl coder generate sequential logic?

Answer 1

[Sachin Ganjare]

I think it is possible, take a look at the link below:

http://www.businesswire.com/news/home/20121017005011/en/ADDING%C2%A0MULTIMEDIA%C2%A0MathWorks-Updates-Stateflow-Simplify-Control-Logic-Design

http://www.mathworks.in/products/stateflow/description5.html

Hope it helps!!!

Answer 2

[Tim McBrayer]

Yes, HDL Coder is well equipped to create sequential logic. It has capabilities to help you solve your timing constraints as well. You can generate registers with several direct (appearing in Simulink) modeling approaches:

• Delay blocks (unit delay, integer delay, tapped delay, etc.)
• Persistent variables in MATLAB Function blocks
• Stateflow chart states

Other blocks also model state as part of their innate behavior, such as the Discrete Time Integrator block, FFTs, CORDIC trig implementations, and many more. RAMs can be explicitly modeled by using the RAM blocks available in the hdldemolib library.

In addition, HDL Coder has the ability for you to specify additional input or output pipeline registers on blocks and subsystems. These pipeline registers can also be heuristically distributed throughout a subsystem, or partially or fully constrained to their specified location. Any modifications to your base Simulink design are modeled accurately in the generated HDL and accounted for in HDL Coder's automated test bench generation.

The tool has a large array of capabilities designed for the system designer. I urge you to dig deeper into the documentation and learn more about how HDL Coder can help you solve your design issues.