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Problems with multirate simscape electrical model

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Hi everyone,
I'm trying to run a simscape electrical model with two networks (CPU and FPGA) and different sample times. I've inserted two solver configuration blocks (one for each subsystem/network) and I'm using the local solver (Backward Euler). The sample time in both solvers it's different, but when I check the sample time of the model I see that the electrical blocks have the global sample time that is set in the solver.
These are the sample times of my model:
Ts_cpu = 50e-6
Ts_fpga = 10e-6
Solver = 1e-6
Attached to this question you can find how I'm configuring the solver configuration, the configuration parameter of the solver and the timing legend of the model.
Do you know how can I set Ts_cpu for CPU network and Ts_fpga for FPGA network?
Thank you in advance,
Ander.

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Accepted Answer

Joel Van Sickel
Joel Van Sickel on 17 Nov 2020
Hello Ander,
you can have seperate step sizes for your solver configurations. This is what it should look like: (I set one to 1e-3 and one to 1e-4, both backward Euler). see the color of the line coming out of the one network vs the other (red vs green).
I attatched the example but its in 2020b so it might not work for you. Let me know what version you'd life if you want an example. Notice the simscape solver block color in this case is yellow for multi-rate, I am not sure that's how it works for older versions.
Regards,
Joel

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Ander Erroicenea
Ander Erroicenea on 18 Nov 2020
It's been really helpful for me, but I see that in your example the electrical blocks (resistors, capacitors...) run at a continuous step time which is set in the solver. Is it possible to run these blocks with the sample time that you set on the solver configuration block?
Regards,
Ander.
Joel Van Sickel
Joel Van Sickel on 18 Nov 2020
Hello Ander,
all simscape components run according to their local solver settings, so the solver configuration overrides anything from the global settings. You can see that my networks are running fixed step by the color of the simulink signal coming out of the ps -> Simulink blocks (see highlights in picture above). That means that in the model I shared is already running fixed step according to the solver configuraiton block, and each network has a different step size. You can change the simulink sover to fixed step, but it won't change how the simscape networks are simulated, only how the simulink model connected to them is simulated (because I've turned on local solver). If you don't turn on local solvers, then they will use the simulink settings and you have to use a more advanced solver that can support simscape networks (such as ode23T or DAESSC). With the local solver on, you can actually use a fixed step discrete solver which is the most efficient solver.
On a seperate note, you will need to set up partitions for the CPU and FPGA portions of the model. I recommend putting everyhing for FPGA inside the same subsystem (with only simulink signals for inputs and outputs), then you can right click this block and use the hdl workflow advisor (also go to hdl block properties and turn on the setting for flatten hierarchy to make life easier). The CPU section of the model could be placed inside a model reference, also with only simulink signals for inputs and outputs. The unit delays can be left external to both systems because they will be forced into existence by the delay between communication between FPGA and CPU.
Regards,
Joel
Ander Erroicenea
Ander Erroicenea on 18 Nov 2020
Hi Joel,
Thank you for this information, now I've understood everything better.
Regards,
Ander.

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