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HDL coder multicycle path constraint question

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Alex Aronov
Alex Aronov on 29 Nov 2020
Answered: Aman Vyas on 16 Dec 2020
I need to constraint multicycle paths in my design.
HDL Coder generates .XDC file for me with the following syntax:
# Multicycle constraints for clock enable: LTA_detector_tc.u1_d2_o0
set enbregcell [get_cells -hier -filter {mcp_info=="LTA_detector_tc.u1_d2_o0"}]
set enbregnet [get_nets -of_objects [get_pins -of_objects $enbregcell -filter {DIRECTION == OUT}]]
set reglist [get_cells -of [filter [all_fanout -flat -endpoints_only $enbregnet] IS_ENABLE]]
set_multicycle_path 2 -setup -from $reglist -to $reglist -quiet
set_multicycle_path 1 -hold -from $reglist -to $reglist -quiet
This constraint works fine, except that Vivado has limitation of 10,000 path per a multicycle path constraint.
My design has much more than 10,000 paths, therefore the constraint works partially and it is not good enough to meet timing.
To solve the problem I need to split this into subsets with less than 10,000 path in each subset.
Does anyone know how to split this constraint?
Thank you,
alex

Answers (1)

Aman Vyas
Aman Vyas on 16 Dec 2020
Hi,
The multipath cycle constraints can be splitted up by splitting he design into some format like you can split the design in form of IP's if it is a very bigger design.
1) Correspondingly you can start generating constraints at IP level and then once you have all the IPs done , then integrate them with flip flops inserted in between them
2) Also if IP level also exceeds 10,000 path , the best you can do is break the design based on different logic paths and then keep on generating constraints and then integrate the design.
3) The best way will be to use some other tools like prime time if your design is of ASIC level and very big where you can generate the constraints from HDL Coder and perform STA (Static Timing Analysis) from Prime time tool.
Hope it helps !

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