Statistics
RANK
142,322
of 300,331
REPUTATION
0
CONTRIBUTIONS
1 Question
1 Answer
ANSWER ACCEPTANCE
0.0%
VOTES RECEIVED
0
RANK
of 20,920
REPUTATION
N/A
AVERAGE RATING
0.00
CONTRIBUTIONS
0 Files
DOWNLOADS
0
ALL TIME DOWNLOADS
0
RANK
of 168,124
CONTRIBUTIONS
0 Problems
0 Solutions
SCORE
0
NUMBER OF BADGES
0
CONTRIBUTIONS
0 Posts
CONTRIBUTIONS
0 Public Channels
AVERAGE RATING
CONTRIBUTIONS
0 Highlights
AVERAGE NO. OF LIKES
Feeds
Answered
HDL Verifier and FPGA in the loop
Did not receive version information from the hardware. You must have a valid connection, a compatible development board, and co...
HDL Verifier and FPGA in the loop
Did not receive version information from the hardware. You must have a valid connection, a compatible development board, and co...
5 years ago | 0
Question
Set up HDL verifier
how can i fix this problem? PS: I work with MATLAB 2019b, Quartus Prime 18.1 & FPGA cyclone IV GX.
5 years ago | 1 answer | 0
