William Knox
Followers: 0 Following: 0
Professional Interests: control, signal processing
Statistics
RANK
12,574
of 292,709
REPUTATION
4
CONTRIBUTIONS
2 Questions
3 Answers
ANSWER ACCEPTANCE
100.0%
VOTES RECEIVED
2
RANK
of 19,934
REPUTATION
N/A
AVERAGE RATING
0.00
CONTRIBUTIONS
0 Files
DOWNLOADS
0
ALL TIME DOWNLOADS
0
RANK
of 147,871
CONTRIBUTIONS
0 Problems
0 Solutions
SCORE
0
NUMBER OF BADGES
0
CONTRIBUTIONS
0 Posts
CONTRIBUTIONS
0 Public Channels
AVERAGE RATING
CONTRIBUTIONS
0 Highlights
AVERAGE NO. OF LIKES
Feeds
Simulink to VHDL using VHDL Coder but "Data Type Conversion" blocks don't compile
To generate HDL code for a subsystem right-click on it and choose "Generate HDL Code for Subsystem". If you right click on th...
12 years ago | 0
Using non-memory-mapped (NMM) ports with FPGA-in-the-loop (FIL) cosim with XUP Atlys Spartan 6 Dev Board
Hi All, I found the solution. To manually create NMM ports perform the following steps; we will be creating a NMM port for th...
12 years ago | 1
| accepted
Digilent XUP Atlys Spartan 6 Development Board support in Hardware Co-Simulation
Hi All, I have found the solution. Xilinx University Program (XUP) provides a Hardware Cosim via point-to-point Ethernet plu...
12 years ago | 1
| accepted
Question
Digilent XUP Atlys Spartan 6 Development Board support in Hardware Co-Simulation
Hi, Does anyone know if The Mathworks plans to support the Digilent XUP Atlys Spartan 6 Development Board in *ethernet-based*...
12 years ago | 1 answer | 0
1
answerQuestion
Using non-memory-mapped (NMM) ports with FPGA-in-the-loop (FIL) cosim with XUP Atlys Spartan 6 Dev Board
Hi, I have a Digilent XUP Atlys Spartan 6 development board. FIL is supported with this board, however there does not seem to ...
12 years ago | 1 answer | 0