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Grégory SEABRA


ASSYSTEM

Active since 2015

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[HDL Coder] How to keep subsystems port names when applying input/output pipelining
Hello, I am currently developping a control algorithm which will be implemented inside a Xilinx Spartan6 FPGA. I generate the...

7 years ago | 1 answer | 0

1

answer

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HDL Coder Workflow Advisor timing analysis
Hello! I am currently working on a project for which my task is to develop a control algorithm for a power converter. This alg...

7 years ago | 1 answer | 0

1

answer