![photo](/responsive_image/150/150/0/0/0/cache/matlabcentral/profiles/32897145_1707127706909_DEF.jpg)
Shalini
Followers: 0 Following: 0
Statistics
3 Questions
0 Answers
RANK
234,209
of 293,595
REPUTATION
0
CONTRIBUTIONS
3 Questions
0 Answers
ANSWER ACCEPTANCE
0.0%
VOTES RECEIVED
0
RANK
of 20,050
REPUTATION
N/A
AVERAGE RATING
0.00
CONTRIBUTIONS
0 Files
DOWNLOADS
0
ALL TIME DOWNLOADS
0
RANK
of 149,446
CONTRIBUTIONS
0 Problems
0 Solutions
SCORE
0
NUMBER OF BADGES
0
CONTRIBUTIONS
0 Posts
CONTRIBUTIONS
0 Public Channels
AVERAGE RATING
CONTRIBUTIONS
0 Highlights
AVERAGE NO. OF LIKES
Feeds
Question
FPGA-in-the-Loop(FIL) validation fails when FPGA board is included in the test using board IP address
I have created a custom board for SP701 FPGA. FIL validation without including board was successful but when the board is includ...
5 months ago | 1 answer | 0
1
answerQuestion
FPGA Turnkey doesn't update Xilinx Vivado as synthesis tool even after setting tool path
I have created a custom board for SP701 FPGA. I'm trying to use Vivado as synthesis tool for FPGA turnkey workflow. But I'm gett...
5 months ago | 1 answer | 0
1
answerQuestion
Auto code generation in matlab simulink for TI2838x board choosing Cortex-M4 as processor and flashing it using CCS
I have created a simple simulink model to send data via ethernet-udp. I need to generate a CCS project file for this model. I ch...
7 months ago | 0 answers | 0