Signal Integrity

What Is Signal Integrity?

Signal integrity is the measure of the quality of an electrical signal as it travels from a source to its intended destination. It refers to the ability of the signal to maintain its intended shape and timing characteristics despite various types of disturbances.

Signal integrity is crucial because it ensures that the data transmission is accurate, reliable, and immune to unwanted effects such as noise, distortion, and reflections. A lack of it can lead to erroneous data transmission, which can cause system failures and significant financial losses.

To ensure proper signal integrity, engineers use MATLAB® and Simulink® to run simulations and perform various analyses. These simulations and analyses help detect potential issues before the system is implemented, thus saving time, resources, and money. Engineers can also use MATLAB to design and verify equalization systems and optimize signal quality.

Key elements:

  • Pre-layout analysis: Perform signal integrity analysis, for both high-speed serial and parallel links, before PCB layout helps identify issues that can arise during design implementation.
  • Post-layout verification: Verify the signal integrity after layout, which allows the identification of issues resulting from different factors such as routing and components.
  • IBIS-AMI models: Use models to simulate high-speed, complex interfaces between integrated circuits, memory, or systems.
  • Signal integrity visualizations: Use metrics such as attenuation, timing jitter, and eye diagrams to measure signal quality and identify problems with signal distortion.

For more information on signal integrity analysis, MathWorks offers a collection of tools including Signal Integrity Toolbox™, SerDes Toolbox™, RF PCB Toolbox™, and Mixed-Signal Blockset™, which provide a suite of features ranging from pre-layout analysis to post-layout verification of a system while producing visualizations such as eye diagrams, waveform plots, frequency spectra, eye contours, and skew budget analysis. These tools provide comprehensive means to prevent issues in data communication systems or high-speed electronics.

Pre-Layout Analysis

One critical step in achieving good signal integrity is performing pre-layout analysis. This analysis is typically done during the design phase and aims to identify potential issues and help engineers make informed decisions that optimize the design.

An example pre-layout schematic sheet from the OIF CEI 25G-LR compliance kit that contains transmitters, receivers, and S-parameters of package and channel models.

OIF CEI 25G-LR pre-layout schematic in the Serial Link Designer app from Signal Integrity Toolbox for use with MATLAB.

By performing pre-layout analysis, engineers can spot and resolve potential issues early in the design cycle, reducing the risk of costly design revisions and modifications later on. This analysis also helps designers optimize the design for signal integrity, resulting in a more robust and reliable design that is compliant with industry standards.

Post-Layout Verification

Post-layout verification involves reviewing the physical implementation of the design, including the actual PCB layout and routing, to ensure that it meets the expected signal integrity performance. The process involves using simulation and analysis tools, such as Signal Integrity Toolbox, to simulate the electrical behavior of the final design and identify any potential issues.

During post-layout verification, engineers may perform simulations to calculate the timing, voltage levels, and signal integrity metrics such as jitter, eye diagram, and bit error rate (BER) to validate the design’s performance and ensure it meets industry standards.

If any signal integrity issues are identified, engineers may make modifications to the layout, routing, or component selection, and rerun the simulations until the design meets the expected performance. In some cases, post-layout verification may reveal issues that were not identified during pre-layout analysis, and engineers must make necessary changes to meet the design requirements.

An example printed circuit board in Signal Integrity Toolbox’s Signal Integrity Viewer app for post-layout verification.

Printed circuit board as shown in the Signal Integrity Viewer app from Signal Integrity Toolbox.

IBIS-AMI Models for Channel Analysis

IBIS-AMI (I/O Buffer Information Specification–Algorithmic Modeling Interface) is a modeling standard used for both pre-layout analysis and post-layout verification of high-speed channels. IBIS-AMI combines the electrical properties of individual components within a signal path to form a complete channel model, enabling engineers to simulate complex high-speed digital systems with greater accuracy and efficiency.

 Example diagrams of transmitters and receivers for IBIS-AMI models from Signal Integrity Toolbox, SerDes Designer app in SerDes Toolbox, and Simulink.

IBIS-AMI models of a SerDes shown as shown in Signal Integrity Toolbox, the SerDes Designer app, and Simulink, respectively.

Using IBIS-AMI models in both pre- and post-layout analysis can help to optimize design time, reduce the risk of design errors, and improve the overall performance of high-speed digital systems. However, creating accurate and reliable IBIS-AMI models can be a complex and time-consuming process, requiring technical expertise and specialized software tools, such as SerDes Toolbox.

Signal Integrity Visualizations

In high-speed digital design, it’s essential to ensure that signals remain intact during transmission to achieve good signal integrity performance. To assess it, various metrics and visualizations are used, including:

  • Voltage margin measures the difference between the amplitude of the signal and the signal’s noise margin. The voltage margin should be sufficiently high to ensure that the signal can be reliably demodulated at the receiver.
  • Timing analysis involves calculating the signal’s rise and fall times, propagation delay, and jitter. Engineers use timing analysis to evaluate the design’s timing budget and ensure that the signal transitions within the required timing window.
  • Jitter is the variation in the signal’s timing over time. Jitter can result from a variety of sources, including signal distortion, crosstalk, power supply noise, and attenuation. Engineers use jitter histograms and eye diagrams to identify and analyze jitter in high-speed digital systems.
  • Eye diagrams are used to analyze the signal’s performance over time and identify potential signal integrity issues. They involve plotting a graph of the signal’s amplitude against time, usually in the form of a histogram. This visualization technique provides a comprehensive view of the signal’s behavior, including jitter, noise, and timing issues.
  • Bit error rate (BER) calculates the number of erroneous bits in a data stream. A high BER value indicates poor signal integrity performance. Engineers use BER to quantify the design’s performance and optimize the design.
  • Attenuation is a measure of signal loss over distance or time. High levels of attenuation can result in signal distortion and signal failure. Engineers use attenuation measurements to evaluate the signal’s performance and design transmission lines and circuits to minimize attenuation.
  • Crosstalk occurs when one signal’s electrical field induces noise into an adjacent signal. Engineers use crosstalk measurements to evaluate the level of interference between channels, calculate the crosstalk coupling coefficient, and identify design methods to reduce the crosstalk level.
  • Time-domain reflectometry (TDR) is an analysis technique used to measure the impedance of a transmission line. TDR compares the signal’s output with the input signal reflected from the end of the line. This technique helps to locate impedance variations and signal integrity issues along transmission lines.
  • Channel Operating Margin (COM) quantifies the design’s margin between the signal’s eye and the worst-case impairments. COM helps engineers evaluate the design’s signal integrity performance and identify areas for improvement.
An example waveform along with the threshold and parameter measurements taken in the Parallel Link Designer app.

Example waveform showing thresholds and parameters measured in the Parallel Link Designer app in Signal Integrity Toolbox.

A PAM3 eye diagram for a USB4 v2.0 system shown in the Signal Integrity Viewer app.

PAM3 eye diagram created with Signal Integrity Toolbox and shown in the Signal Integrity Viewer app.

Software Reference

See also: SerDes toolbox, RF PCB Toolbox, RF Toolbox, Mixed-Signal Blockset, mixed-signal systems, IBIS-AMI models, S-parameters, convolution, fast Fourier transform (FFT), Signal Integrity Toolbox, serdes