addRegisterInterface

R2026b

Class: hdlcoder.ReferenceDesign
Namespace: hdlcoder

Add and define register interface using AXI4 and AXI4-Lite protocol

Syntax

addRegisterInterface(InterfaceConnection=ref_design_port,BaseAddress=base_addr)
addRegisterInterface(InterfaceConnection=ref_design_port,BaseAddress=base_addr,MasterAddressSpace=master_addr_space)
addRegisterInterface(InterfaceConnection=ref_design_port,BaseAddress=base_addr,Name=Value)
addRegisterInterface(InterfaceConnection=ref_design_port,BaseAddress=base_addr,MasterAddressSpace=master_addr_space,Name=Value)


Description

addRegisterInterface(InterfaceConnection=ref_design_port,BaseAddress=base_addr) adds and defines an AXI4 interface for an Altera^® reference design or an AXI4 or AXI4-Lite interface for a Xilinx^® ISE reference design.

addRegisterInterface(InterfaceConnection=ref_design_port,BaseAddress=base_addr,MasterAddressSpace=master_addr_space) adds and defines an AXI4 or AXI4-Lite interface for Xilinx Vivado^® reference designs.

addRegisterInterface(InterfaceConnection=ref_design_port,BaseAddress=base_addr,Name=Value) adds and defines an AXI4 interface for an Altera reference design or an AXI4 or AXI4-Lite interface for a Xilinx ISE reference design, with additional options specified by one or more name-value arguments.

addRegisterInterface(InterfaceConnection=ref_design_port,BaseAddress=base_addr,MasterAddressSpace=master_addr_space,Name=Value) adds and defines an AXI4 or AXI4-Lite interface for Xilinx Vivado reference designs, with additional options specified by one or more name-value arguments.

Input Arguments

ref_design_port — Reference design port name

'' (default) | character vector

Reference design port that is connected to the AXI4 or AXI4-Lite interface, specified as a character vector. For reference designs based on Intel^® Qsys™, when you want to connect multiple AXI Master IPs to the AXI4 or AXI4-Lite interface, specify each of the AXI Master instance names and the corresponding port names as a cell array of character vectors.

Example: 'axi_interconnect_0/M00_AXI', {'hps_0.h2f_axi_master','master_0.master'},...

base_addr — Base address

'' (default) | character vector

Base address for AXI4 or AXI4-Lite register interface, specified as a character vector.

Example: '0x40010000'

master_addr_space — Master interface address space (Vivado only)

'' (default) | character vector

Address space of the master interface connected to this register interface, specified as a character vector. For Vivado reference designs only. When you want to connect more than one AXI Master IP, specify each of the AXI Master instance names and the corresponding address spaces.

Example: 'processing_system7_0/Data', {'processing_system7_0/Data','hdlverifier_axi_master_0/axi4m'}

Name-Value Pair Arguments

Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

InterfaceType — Interface type

{'AXI4-Lite','AXI4'} (default) | 'AXI4' | 'AXI4-Lite'

Type of interface connection, specified as a character vector or a cell array of character vectors.

Example: InterfaceType='AXI4-Lite' specifies an 'AXI4–Lite' interface type connection.

InterfaceID — Interface name

{'AXI4-Lite','AXI4'} (default) | character vector

Name of the interface, specified as a character vector. When you provide the InterfaceID, InterfaceType must be set to either 'AXI4' or 'AXI4–Lite'.

Example: InterfaceID='MyAXI4',InterfaceType='AXI4' specifies interface name as 'MyAXI4' and interface type as 'AXI4'.

IDWidth — Width of ID signals

positive integer

IDWidth is the width of all ID signals, such as AWID, WID, ARID, and RID, specified as a positive integer. The ID width only applies when you use the AXI4 interface and does not apply for the AXI4-Lite interface.

The ID width value is tool-specific, and may need to increase when the AXI4 register interface on the DUT IP core is connected to multiple master interfaces. If you specify a value and enable the Insert AXI Manager parameter, HDL Coder™ increments the ID with value by one. if you do not specify the ID width, HDL Coder attempts to calculate the correct ID with based on the number of masters in the design.

Example: IDWidth=13

HasProcessorConnection — Indicate register connection to processor

true (default) | false | logical data type

Indicate if the processor is one of the masters to the IP core AXI4 register interface. To enable device tree generation for the IP core register interface, keep this value set to true.

Example: HasProcessorConnection=false

DeviceTreeBusNode — Reference to processor AXI4 master bus node in the device tree

" " (default) | string | character vector

Reference to the processor AXI4 master bus node in the device tree. Set this value to match the name of the corresponding bus node in the registered device tree. References to device tree nodes must start with "&". To reference a node by its label, specify "&" before the label, such as "&myLabel". To reference a node by its path, specify the path inside "&{" and "}", such as "&{/myNode/childNode}".

Example: DeviceTreeBusNode='&fpga_axi'

DesignFragment — Design fragment files to source into generated Vivado project

{} (default) | cell array

Design fragment files to source into the generated Vivado project, specified as a cell array. Use this argument to add hardware components that are required only when the AXI4 or AXI4-Lite interface is mapped, such as AXI Interconnect, peripheral IP cores, or other register-accessible hardware.

Specify file names relative to the reference design plugin folder, as absolute paths, or relative to folders added by using addIncludeFolder. If the file is located in an added folder, you can specify only the file name.

This argument supports only Xilinx Vivado reference designs. The design fragment files must use the .tcl extension. The generated project sources the specified files after the base custom block design TCL file and includes them only when the AXI4 or AXI4-Lite interface is mapped.

Example: DesignFragment={"shared\led_peripheral.tcl"} specifies a file name relative to the reference design plugin folder.

Example: DesignFragment={"C:\work\tcl\led_peripheral.tcl"} specifies an absolute file path.

Example: DesignFragment={"led_peripheral.tcl"} specifies a file in a folder added by using addIncludeFolder.

DeviceTreeFragment — Device tree fragment files to append to generated Linux device tree

{} (default) | cell array

Device tree fragment files to append to the generated Linux^® device tree, specified as a cell array. Use this argument to describe register-accessible hardware associated with the AXI4 or AXI4-Lite interface, such as peripheral nodes, address regions, or driver-specific properties.

Specify file names relative to the reference design plugin folder, as absolute paths, or relative to folders added by using addIncludeFolder. If the file is located in an added folder, you can specify only the file name.

This argument supports only Xilinx Vivado reference designs. The device tree fragment files must use the .dts or .dtsi extension. The generated device tree appends the specified files and includes them only when the AXI4 or AXI4-Lite interface is mapped.

Example: DeviceTreeFragment={"shared\led_peripheral.dtsi"} specifies a file name relative to the reference design plugin folder.

Example: DeviceTreeFragment={"C:\work\devicetrees\led_peripheral.dtsi"} specifies an absolute file path.

Example: DeviceTreeFragment={"led_peripheral.dtsi"} specifies a file in a folder added by using addIncludeFolder.

ConstraintFragment — Constraint files to add to generated project

{} (default) | cell array

Constraint files to add to the generated project, specified as a cell array. Use this argument to specify constraints associated with hardware introduced by the AXI4 or AXI4-Lite interface, such as pin assignments, I/O standards, or timing exceptions.

Specify file names relative to the reference design plugin folder, as absolute paths, or relative to folders added by using addIncludeFolder. If the file is located in an added folder, you can specify only the file name.

This argument supports only Xilinx Vivado reference designs. The constraint files must use the .xdc extension. The generated project adds the specified files to the project constraint set and includes them only when the AXI4 or AXI4-Lite interface is mapped.

Example: ConstraintFragment={"shared\led_peripheral.xdc"} specifies a file name relative to the reference design plugin folder.

Example: ConstraintFragment={"C:\work\constraints\led_peripheral.xdc"} specifies an absolute file path.

Example: ConstraintFragment={"led_peripheral.xdc"} specifies a file in a folder added by using addIncludeFolder.

Tips

• Before running this method, you must run the addClockInterface method.

• The addRegisterInterface method is optional. You can define your own custom reference design without an AXI4 register interface.

• To connect the HDL IP core for your DUT to multiple AXI Master interfaces in the reference design, use the IDWidth property of this method. To learn more, see Define Multiple AXI Master Interfaces in Reference Designs to Access DUT AXI4 Subordinate Interface.

Version History

Introduced in R2015a

R2026a: Renamed AXI4-Slave elements in HDL Coder

HDL Coder has renamed several function names and user interface elements that previously used the term “slave”. These changes reflect the adoption of inclusive terminology in MathWorks software and documentation.

Functionality Type	Name in Previous Releases	Current Name
Function	addAXI4SlaveInterface	addRegisterInterface
Method	hdlcoder.ReferenceDesign.addAXI4SlaveInterface	hdlcoder.ReferenceDesign.addRegisterInterface