Define Custom Board and Reference Design for AMD Kria KR260 Robotics Kit
This example shows how to define and register a custom board and reference design for the AMD® Kria® KR260 Robotics Starter Kit. You create a reference design that controls the LEDs on the board and use this reference design to generate an IP core and deploy your design on the Kria board. You can use this example to define custom boards and reference designs for other Zynq® UltraScale+ MPSoC platforms.
Requirements
To run this example, you need:
The Xilinx® Vivado® Design suite. For a list of supported versions, see HDL Language Support and Supported Third-Party Tools and Hardware.
The AMD Kria KR260 Robotics Starter Kit.
HDL Coder Support Package for AMD FPGA and SoC Devices.
Create and Export Custom Reference Design Using Xilinx Vivado
A reference design is an example project that shows how different parts of a system connect. Use HDL Coder to generate a custom IP core that integrates with this reference design. You can then use the combined design to create a Vivado project, generate a bitstream, and program the target hardware. The figure illustrates the relationship between the reference design, the IP core, and the hardware board.
To create and export a reference design by using Xilinx Vivado, follow these steps:
1. Open Xilinx Vivado and create an RTL project by adding the necessary source files and the constraint files. In the board selection step, click the Boards tab and select AMD Kria KR260 Robotics Starter Kit SOM as the target device. If you want to add the companion card and manage the connections to the SOM, click the Connections option as shown below.
2. To create a block design in Vivado, click the Create Block Design option in the IP Integrator drop-down list. If you want your programming logic (PL) to communicate with the processing system (PS), add the Zynq UltraScale+ MPSoC Processing System IP block to the block design. After adding the PS IP block, run the block automation.
3. To set the board preset on the PS for Kria KR260 Robotics Starter Kit, select the Apply Board Preset check box. After applying the board preset, the block design marks the MIO peripherals according to the board definition.
4. Add the required third party IPs or Vivado IPs into your block design. Add these IPs to complete the block design:
Clocking Wizard IP
Processor System Reset IP
AXI Interconnect IP
Note that the block design does not contain any information about the HDL IP core.
5. Export the complete block design as a Tcl script. In the Files tab, click Export and select Export Block Design. Name the Tcl script as system.tcl.
The exported Tcl script contains the custom reference design. You use the Tcl script to recreate the block design and integrate the HDL IP core with the block design in a Xilinx Vivado project.
After exporting the custom reference design to the Tcl script, you can create these custom board files in MATLAB:
The board definition file (
plugin_board.m)The board registration file (
hdlcoder_board_customization)The reference design definition file (
plugin_rd.m)The reference design registration file (
hdlcoder_ref_design_customization)
The figure shows the folder structure for custom board and reference design files. After creating these files, add folder to the MATLAB path before generating IP Core.
Register AMD Kria KR260 Robotics Starter Kit
To register the AMD Kria KR260 Robotics Starter Kit with HDL Coder, create the board definition and board registration files in MATLAB.
Create Board Definition File
Create a board definition file with the name plugin_board.m under the board plugin package folder +KriaKR260. This file contains information about the peripherals present on the board and the corresponding FPGA pin mappings. For more information on the board definition file, see AMD User Guide.
The BoardName property defines the KR260 board name as AMD Kria KR260 Robotics Starter Kit. This name displays in HDL Workflow Advisor and Configuration Parameter dialog box.
function hB = plugin_board() %Copyright 2025 The MathWorks, Inc. % Board definition % Construct board object hB = hdlcoder.Board; hB.BoardName = 'AMD Kria KR260 Robotics Starter Kit'; % FPGA device information hB.FPGAVendor = 'Xilinx'; hB.FPGAFamily = 'Zynq UltraScale+'; hB.FPGADevice = 'xck26-sfvc784-2LV-c'; hB.FPGAPackage = ''; hB.FPGASpeed = ''; % Tool information hB.SupportedTool = {'Xilinx Vivado'}; % FPGA JTAG chain position hB.JTAGChainPosition = 1; % Add interfaces % Custom board external I/O interface hB.addExternalPortInterface( ... 'IOPadConstraint', {'IOSTANDARD = LVCMOS18'}); hB.addExternalIOInterface( ... 'InterfaceID', 'LEDs General Purpose', ... 'InterfaceType', 'OUT', ... 'PortName', 'LEDs', ... 'PortWidth', 2, ... 'FPGAPin', {'F8', 'E8'}, ... 'IOPadConstraint', {'IOSTANDARD = LVCMOS18'}); % Add interfaces % Custom board external I/O interface hB.addExternalIOInterface( ... 'InterfaceID', 'PMOD Connector J2', ... 'InterfaceType', 'OUT', ... 'PortName', 'PMOD-J2', ... 'PortWidth', 8, ... 'FPGAPin', {'H12', 'B10', 'E10', 'E12', 'D10', 'D11', 'C11', 'B11'}, ... 'IOPadConstraint', {'IOSTANDARD = LVCMOS33'}); hB.addExternalIOInterface( ... 'InterfaceID', 'PMOD Connector J18', ... 'InterfaceType', 'OUT', ... 'PortName', 'PMOD-J18', ... 'PortWidth', 8, ... 'FPGAPin', {'J11', 'H11', 'J10', 'G10', 'K13', 'F12', 'K12', 'F11'}, ... 'IOPadConstraint', {'IOSTANDARD = LVCMOS33'}) hB.addExternalIOInterface( ... 'InterfaceID', 'PMOD Connector J19', ... 'InterfaceType', 'OUT', ... 'PortName', 'PMOD-J19', ... 'PortWidth', 8, ... 'FPGAPin', {'AE12','AF11','AF12','AG11','AG10','AH12','AH10','AH11'}, ... 'IOPadConstraint', {'IOSTANDARD = LVCMOS33'}) hB.addExternalIOInterface( ... 'InterfaceID', 'PMOD Connector J20', ... 'InterfaceType', 'OUT', ... 'PortName', 'PMOD-J20', ... 'PortWidth', 8, ... 'FPGAPin', {'AC12','AD11','AD12','AD10','AE10','AA11','AF10','AA10'}, ... 'IOPadConstraint', {'IOSTANDARD = LVCMOS33'}) end
Create Board Registration File
Create a board registration file with the name hdlcoder_board_customization.m. A board registration file contains a list of board plugins. HDL Coder registers boards associated with the board plugin by using the customization file.
function r = hdlcoder_board_customization % Board plugin registration file % 1. Any registration file with this name on MATLAB path will be picked up % 2. Registration file returns a cell array pointing to the location of % the board plug-ins % 3. Board plugin must be a package folder accessible from MATLAB path, % and contains a board definition file % Copyright 2025 The MathWorks, Inc. r = { ... 'KriaKR260.plugin_board', ... }; end
Register Custom Reference Design with HDL Coder
After registering the Kria KR260 board, you can register the reference design with HDL Coder.
Create Reference Design Definition File
Create a reference design definition file with the name plugin_rd.m. A reference design definition file defines the interface connections between the custom reference design and the HDL IP core that is generated by the HDL Coder.
function hRD = plugin_rd() % Copyright 2025 The MathWorks, Inc. % Reference Design definition % Construct Reference Design object hRD = hdlcoder.ReferenceDesign('SynthesisTool', 'Xilinx Vivado'); hRD.ReferenceDesignName = 'Default system'; hRD.BoardName = 'AMD Kria KR260 Robotics Starter Kit'; % Tool information hRD.SupportedToolVersion = {'2024.1'}; % hRD.addCustomVivadoDesign( ... 'CustomBlockDesignTcl', 'system.tcl', ... 'VivadoBoardPart','xilinx.com:kr260_som:part0:1.1'); %Design constraints (optional) hRD.CustomConstraints = {'kria_kr260.xdc'}; %% Add interfaces % Add clock interface hRD.addClockInterface( ... 'ClockConnection', 'core_clkwiz/clk_out1', ... 'ResetConnection', 'sys_core_rstgen/peripheral_aresetn'); % add Register interfaces hRD.addRegisterInterface( ... 'InterfaceConnection', 'axi_cpu_interconnect/M00_AXI', ... 'BaseAddress', '0x00A0000000', ... 'MasterAddressSpace', 'zynq_ultra_ps_e_0/Data'); %% % Default devicetree available on the board hRD.DeviceTreeName = 'system.dtb'; %Enabling the download mode as there is processing system in the design hRD.HasProcessingSystem = true; end
The reference design plugin folder, +vivado_base_2024_1, must also contain the design files, such as, system.tcl, that you export from the Xilinx Vivado project. The reference design definition file plugin_rd.m uses the addCustomVivadoDesign function to identify the SoC design project.
If you want to add design specific constraints, add them to the file kria_kr260.xdc and then add this file to the reference design plugin by using the hRD.CustomConstraints property. For more information about KR260 board constraints, see AMD's website.
The reference design definition file also defines the interface connections between the custom reference design and the HDL IP core by using the addClockInterface and addRegisterInterface functions.
Create Reference Design Registration File
Create a reference design registration file named hdlcoder_ref_design_customization.m that contains a list of reference design plugins associated with the KR260 Robotics Starter kit. A reference design registration file must also contain the name of the associated board.
function [rd, boardName] = hdlcoder_ref_design_customization %Copyright 2025 The MathWorks, Inc. rd = {'KriaKR260.vivado_base_2024_1.plugin_rd', ... }; boardName = 'AMD Kria KR260 Robotics Starter Kit'; end
Set Up AMD Kria KR260 Robotics Starter Kit
To learn more about the AMD Kria KR260 Robotics Starter Kit, see the AMD User Guide. To set up the AMD Kria KR260 Robotics Starter Kit on the board:
1. Connect the shared JTAG or UART port on the board to your computer.
2. Connect the AMD Kria KR260 Robotics Starter Kit to your computer by using an Ethernet cable. You can use top-right PS Ethernet port, GEM0, which is connected to the J10D connector.
3. Download the Kria KR260 Linux image, extract the ZIP archive, and copy the contents to the microSD card.
4. Insert the microSD card into the J11 connector and power on the board.
5. Initially, the board uses the factory-provided BIN file to boot up. After the board boots, run this command at Linux terminal of the board to load the provided MathWorks BOOT.BIN file. For more information on opening the Linux terminal on the target, see Command Line Session with AMD SoC Devices (Embedded Coder).
sudo xmutil bootfw_update -i /mnt/BOOT.BIN
6. To apply the changes, reset the board by using the SW2 reset button. The board boots up with the MathWorks BOOT.BIN file.
7. Ping the board at the 192.168.1.101 IP address. This is the IP address that the MathWorks Linux image uses. You can modify this IP address by updating the interfaces file in the /mnt directory.
Generate HDL Code and IP Core
You can now use the board and reference design plugins to generate the HDL IP core, integrate the IP core into the Vivado project, generate the bitstream, and program the Kria board. For more information, see Get Started with IP Core Generation from Simulink Model.
1. Add the board and reference design plugins to the MATLAB path. Run these commands in the MATLAB Command Window:
example_root = hdlcoder_amd_examples_root
addpath(fullfile(example_root,"KR260"))
2. Set the Xilinx Vivado tool path by using the hdlsetuptoolpath function. Use your own Xilinx Vivado installation path. For more information, see hdlsetuptoolpath.
hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','vivado_installation_path');
3.Open the Simulink model.
open_system('hdlcoder_led_blinking_2bit');
The design under test (DUT) subsystem, led_counter, models a counter that blinks the LEDs on an FPGA board. It has two input ports, Blink_frequency and Blink_direction, which determine the LED blink frequency and direction. The output ports, LED, connects to the user-defined LEDs on the board. The output port Read_back outputs the count value. The board processor sends this value to MATLAB.
4. In the Apps tab, click HDL Coder. To open the Configuration Parameters dialog box, in the HDL Code tab, click Settings. In the HDL Code Generation > Target pane, set:
Workflow to
IP Core GenerationTarget Platform to
AMD Kria KR260 Robotics Starter KitSynthesis Tool to
Xilinx VivadoReference Design to
Default SystemTarget Frequency to 50 MHz
Click OK to save your updated settings.
5. To open the IP Core editor, in the HDL Code tab, click Target Interface. To map each DUT port to the target interfaces, select the Interface Mapping tab.. If no mapping table appears, click the Reload IP Core settings button 
.Map the DUT ports to the interfaces:
For the DUT ports Blink_frequency, Blink_direction, and Read_back, set the cells in the Interface column to
AXI4-Lite.For the LED output port, set the cell in the Interface column to
LEDs General Purpose [0:1].
6. The registers mapped to the DUT inports, Blink_frequency and Blink_direction, are write registers. If you want to read the values stored in the write registers by using devmem, open the Interface Settings tab and select Enable readback on write registers check box. For more information, see Get Started with IP Core Generation from Simulink Model.
7. Validate your settings by clicking the Validate IP Core settings button 
.
8. After you configure the IP core settings and mappings for your design, you can generate an IP core. In the Simulink Toolstrip, in the HDL Code tab, click Generate IP Core. After successful IP Core generation, Code Generation Report opens. Click IP Core Generation Report to see the register address mapping for your DUT ports. For more information, see Custom IP Core Report.
9. Insert the generated IP core into an embedded system reference design by creating a Vivado project and generating an FPGA bitstream. In the HDL Code tab, click Build Bitstream.
Verify Design Using Host Interface Script
You can verify your generated IP core on the hardware by using the MATLAB host interface script. This script contains MATLAB commands that connect your hardware and interact with your IP core. To generate a host interface script file, in the Simulink Toolstrip, in the HDL Code tab, select Host Interface Script > Host Interface Script.
For rapid prototyping, open the gs_hdlcoder_led_blinnking_2bit_interface.m file and modify Blink_frequency and Blink_direction. For more information, see Generate and Manage FPGA I/O Host Interface Scripts
%-------------------------------------------------------------------------- % Host Interface Script % % Generated with MATLAB 26.1 (R2026a) at 12:54:34 on 08/09/2025. % This script was created for the IP Core generated from design 'hdlcoder_led_blinking_2bit'. % % Use this script to access DUT ports in the design that were mapped to compatible IP core interfaces. % You can write to input ports in the design and read from output ports directly from MATLAB. % To write to input ports, use the "writePort" command and specify the port name and input data. The input data will be cast to the DUT port's data type before writing. % To read from output ports, use the "readPort" command and specify the port name. The output data will be returned with the same data type as the DUT port. % Use the "release" command to release MATLAB's control of the hardware resources. %-------------------------------------------------------------------------- %% Program FPGA % Uncomment the lines below to program FPGA hardware with the designated bitstream and configure the processor with the corresponding devicetree. % MATLAB will connect to the board with an SSH connection to program the FPGA. % If you need to change login parameters for your board, use the following syntax: % hProcessor = xilinxsoc(ipAddress, username, password); hProcessor = xilinxsoc('192.168.1.101','root','root'); programFPGA(hProcessor, "hdl_prj\vivado_ip_prj\vivado_prj.runs\impl_1\system_wrapper.bit", "system.dtb"); %% Create fpga object hFPGA = fpga(hProcessor); %% Setup fpga object % This function configures the "fpga" object with the same interfaces as the generated IP core gs_hdlcoder_led_blinking_2bit_setup(hFPGA); %% Write/read DUT ports % Uncomment the following lines to write/read DUT ports in the generated IP Core. % Update the example data in the write commands with meaningful data to write to the DUT. %% AXI4-Lite writePort(hFPGA, "Blink_frequency",3); writePort(hFPGA, "Blink_direction", zeros([1 1])); data_Read_back = readPort(hFPGA, "Read_back"); % % %% Release hardware resources release(hFPGA);
When you run this script, HDL Coder creates an application with the name mw_hdlcoder_K26 on the target and loads the design to the FPGA. When you run the script, the user-defined LEDs, F8 and E8, blink on the KR260 kit.
To check whether the application was created on the target, use this Kria utility command:
sudo xmutil listapps
You do not need to program the target each time you prototype your design. After programming the target once, you can comment out the programFPGA API. To change the LED blink rate, modify the Blink_frequency register value in the script.
Control the AXI4-Lite Registers by Using the devmem Command
In the script, the blink frequency is set 3. You can verify this on the target by using the devmem command. The register address for Blink_frequency is 0xA0000100, which is the base address, 0xA0000000, combined with the address offset, 0x00000100. The base address is the value you defined for your HDL IP core in the plugin_rd.m file. The address offset is the address that HDL Coder assigns to this register in Interface Mapping tab. You can also view this information in the IP core generation report.
You can also change the blink frequency by using the devmem command. Change the frequency to 5.
The LEDs blink faster.
See Also
Register a Custom Board | Register a Custom Reference Design
