MATLAB stuck when HDL coder converted the model to Verilog
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After clicking henerate HDL code to run, the operation page is directly stuck and no operation can be carried out. MATLAB can only be forcibly closed. And no Verilog was produced。

If I close MATLAB directly, the following error report will appear. But if I wait for it to run, MATLAB will jam.

So when I changed the output to multiple parallel structures, and I continued to run henerate HDL code, the program, just like it did before, just stuck. Continue to close MATLAB, at this time a new error.

error:Compilation errors when generating code for: Matrix/jvzhen\Selector1 Error during MATLAB code compilation: Error Path: B:\matlab\src\cgir_hdl\emlinterface\EMLInterfaceForHDL.cpp:407 Error Location: (@Row: --> 5 @Column: --> 14) Compilation aborted by user. Internal Error: This error occurred inside a MathWorks function.
Answers (1)
Kiran Kintali
on 22 Feb 2023
0 votes
Can you share your model or reach out to tech support for further guidance on the topic?
In general this model seems to be using large matrices at the IO. You have two options.
- Manual frame to sample conversion; reduce the IO usage by passing samples into the dut; use additional valid, ready signals to control the IO frames.
mlhdlc_demo_setup('heq')
- Use to automated frame to sample conversion workflow
10 Comments
wang
on 23 Feb 2023
wang
on 28 Feb 2023
Kiran Kintali
on 28 Feb 2023
Feel free to reach out with a model for additional recommendations.
wang
on 1 Mar 2023
Kiran Kintali
on 1 Mar 2023
Please reach out to MathWorks support with reproduction steps. The model does not compile.
Error using slhdlcoder.SimulinkConnection/initModel
Invalid setting in 'jvzhen/unit8Fcn' for parameter 'm'
wang
on 6 Mar 2023
Arash Jafari
on 20 Nov 2023
I have the same problem as I use the CIC decimation HDL optimized simulink block in my model. Since this block only accepts vectorized data as input, if the user sets the decimation factor to 20 the HDL coder gets stuck in the VHDL code generation.
you wrote"Manual frame to sample conversion; reduce the IO usage by passing samples into the dut; use additional valid, ready signals to control the IO frames" I could not find a way to apply a manual frame to sample conversion in combination with CIC decimation HDL optimized Simulink block
The automatic I/O optimization and frame-to-sample conversion are introduced in R2022b and R2023 and I'm using R2021a.
Any comment is highly appreciated.
Kind regards
Arash
Kiran Kintali
on 20 Nov 2023
Edited: Kiran Kintali
on 20 Nov 2023
Arash, Would you be able to share a sample model? Thanks.
Kiran Kintali
on 20 Nov 2023
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