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Kiran Kintali


Last seen: 1 day ago

MathWorks

220 total contributions since 2011

Professional Interests: Signal Processing, FPGAs and ESL Design

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  • Knowledgeable Level 3
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Answered
Are there enough resources in a Kintex7 160T for my Simscape Electrical model ?
Can you share a mat file with A,B,C,D,F0,Y0 values shown above? It depends if the matrix is largely sparse or has all non-zero v...

2 days ago | 0

Answered
hdlsetuptoolpath miss (not exist) FPGA, Xilinx, HDL Coder,
There seems to be a problem with HDLCoder product installation. Reinstalling the product and checking for valid license would he...

2 days ago | 0

Answered
How to control HDL QPSK Modem with Analog Devices No-OS Software
Analog Devices Engineer Zone - have a forum for no-OS drivers at https://ez.analog.com/microcontroller-no-os-drivers/. ADI’s T...

3 days ago | 0

Answered
HDL Coder Flatten Hierachy does not work with masked library block
Will you be able to provide a model with reproduction steps? I suspect this is related to failure to do delay balancing due to ...

8 days ago | 0

Answered
Wrap Xilinx IP in Simulink black box
>> I am asking how to wrap my HDL code in a block for use in Simulink Hi Talon, Have you checked this feature which clearly de...

9 days ago | 0

Answered
Wrap Xilinx IP in Simulink black box
https://www.mathworks.com/help/hdlcoder/examples/using-xilinx-system-generator-for-dsp-with-hdl-coder.html Using the Xilinx Sys...

11 days ago | 0

Answered
HDL Coder. Undefined function or variable '***'. The first assignment to a local variable determines its class.
Hi Salvador, Can you share a testbench file for this design? Test bench determines the compute the input types used to compile t...

11 days ago | 0

Answered
Can't Get Rid of UseMatrixTypesInHDL Warning
This is not exepcted behavior. Please reach out to support@mathworks.com for additional help. In 20b pre-release this option is...

14 days ago | 0

Answered
Complex to Magnitude-Angle HDL Optimized does not get converted to clock-rate
The "Complex to Magnitude-Angle HDL Optimized" simulates latency in the original model and does not participate in clock rate pi...

19 days ago | 1

| accepted

Answered
Failed to program the device of the Zedboard Using matlab R2019b
Hi Yuhwai, This is unexpected. Please report the issue to support@mathworks.com for further support.

20 days ago | 0

Answered
Error "Brace indexing ist not supported for variables of this type" in HDL Workflow Advisor
Hi Niklas, This is unexpected. Please report the issue to support@mathworks.com for further support.

20 days ago | 0

Answered
How to optimize multiplications with hdl coder
ConstMultiplierOptimization The ConstMultiplierOptimization implementation parameter lets you specify use of canonical signed d...

22 days ago | 1

Answered
What is the good manner of generating the HDL Code of a mixed Simscape/Simulink model ?
Simscape Hardware-in-the-Loop Workflow Automatic replacement of Simscape subsystem with state-space implementation In R2020b, ...

23 days ago | 1

| accepted

Answered
Internal Error in generation of HDL IP core for a Xilinx platform
Can you explain why you would need to force the subsystem to be atomic for Zynq targeting? I totally understand the additional ...

23 days ago | 0

Answered
Internal Error in generation of HDL IP core for a Xilinx platform
Firstly, you need to fix algebraic loop option on the FPGA DUT by turning off this option as follows set_param('PID_example2...

25 days ago | 0

Answered
How can i generate testbench data for fixed point range
Hi, for better guidance, can you share your sample model that you plan to take to HDL code generation? Thanks.

28 days ago | 0

Answered
How to connect bus data type to external port interface?
Bus support for External Port is not yet supported in HDLCoder and is under active development and will be available in the near...

1 month ago | 0

Answered
Why it occur overflow??
The overflow behavior is based on what kinds of operations are happening on the variable. Is it in a feedback look like a for-lo...

1 month ago | 0

Answered
CWT Filter Bank Function
Generating code FPGA cannot support variable dimensions as HDLCoder needs to generate code for a chip with fixed size, type, dim...

1 month ago | 0

Answered
Is there a way to change the parameter in simulink??
Have you considered using to workspace and from workspace blocks and logging your time series data and reading it back in?

1 month ago | 0

| accepted

Answered
Is there a 'block' similar to MATLAB's 'persistent' in simulink??
I am not using any new Simulink features; so you can try to load the model in your version. Try this to load the model. >> s...

1 month ago | 1

Answered
Is there a 'block' similar to MATLAB's 'persistent' in simulink??
Attached model shows how to model unit delay, integer delay, tapped delay in MALTAB and corresponding blocks/modeling patterns i...

1 month ago | 0

Answered
HDL Workflow Advisor error
Hi, This is an unexpected internal error. Can you share the model?

1 month ago | 0

| accepted

Answered
HDL Coder returns with error "Unrecognized fixed-point encoding"
can you reach out to support@mathworks.com to help debug this error further? thanks

1 month ago | 0

Answered
Codegen parfor + singleC
parfor support is an active area of development for -singleC feature; please feel free to reach out to us support@mathworks.co...

2 months ago | 0

Answered
Cell arrays are not supported when using the -singleC flag (Coder)
cell array support is an active area of development for -singleC feature; please feel free to reach out to us support@mathwork...

2 months ago | 0

Answered
Matlab Options for Programming Labview R-series FPGA card.
Please let us know if this tutorial is somethign that can be used in your case. MATLAB®, Simulink®, and LabVIEW FPGA: Importing...

2 months ago | 0

Answered
HDL Coder returns with error "Unrecognized fixed-point encoding"
Hi Tim, Based on the error message this does not seem to be coming during code generation process. Are you sure you able to com...

2 months ago | 0

Answered
HDL code generation from simulink and dumping process
The question is a bit vague; can you provide more specifcis on your workflow issues? HDLCoder should support cyclone V workflo...

2 months ago | 0

Answered
how to use exp funnction in hdl coder?
Hi, Can you add more details and share example files with projects and reproductions here so that we can give better guidance?...

2 months ago | 0

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