Community Profile

photo

Kiran Kintali


Last seen: 5 days ago

MathWorks

289 total contributions since 2011

Professional Interests: Signal Processing, FPGAs and ESL Design

Contact

Kiran Kintali's Badges

  • Revival Level 3
  • 12 Month Streak
  • 5-Star Galaxy Level 4
  • Personal Best Downloads Level 2
  • First Review
  • First Submission
  • Knowledgeable Level 3
  • First Answer

View details...

Contributions in
View by

Answered
DE-10 Nano development kit
Board and Reference Design Registration System System for defining and registering boards and reference designs. Register a Cu...

7 days ago | 0

Answered
Error when I click on build model in SIMULINK
This seems to be Xilinx ISE synthesis tool installation issue; please check your installation and contact Xilinx customer suppor...

10 days ago | 0

Answered
Error in simulnk: Action types are not supported
This question has two parts: Does HDL Coder currently support "Fuzzy Logic Controller"? Does HDL Coder support "If" Action su...

10 days ago | 0

Answered
How to do speed optimizations with/in feedback Loops? -Simulink HDL Coder
To address pipelining of blocks in feedback loops you can refer to this example and related HDL Coder features. https://www.mat...

11 days ago | 0

Answered
timing loops found by synthesis tool when using sqrt function block in hdl coder
This is now fully resolved in R2020b release. Sqrt operation is fully pipelined and several custom latency options for a range o...

11 days ago | 1

Answered
HDLコード変換した演算ブロックの動作について
(Translation) When HDL code is generated for a Simulink model in HDL Coder (native floating point mode) It seems that the code ...

11 days ago | 0

Answered
Is there something like code replacement when using HDL Coder?
The simplest approach for incorporating external IP into your HDL Coder Design is to create a black box interface for a subs...

11 days ago | 0

Answered
How to use genetic xilinx platform in HDL coder.
To support any new board, you need to build a custom reference design. https://www.mathworks.com/help/supportpkg/xilinxzynq7000...

11 days ago | 0

Answered
Matlab to vhdl conversion
HDL Coder supports a single entry point called DUT from which VHDL/Verilog is generated. Consider making one top level dut.m f...

12 days ago | 0

Answered
Importhdl function model generation failed. Assertion failed
If the issue is still reproducible in R2020b please share the sample verilog module.

12 days ago | 0

Answered
HDL coder random generator
Please see the suggestion in this post.

12 days ago | 0

Answered
HDL Coder: How to multiply floating point numbers in a stateflow project?
HDL Coder does not support Stateflow models with floating-point Math in actions. Please consider using MATLAB Function block wit...

12 days ago | 0

Answered
How can I convert my Matlab code of Image Fusion into vhdl code and then dump it into fpga kit
Please check this example for the workflow using HDL Coder. https://www.mathworks.com/help/hdlcoder/ug/image-enhancement-by-his...

12 days ago | 0

Answered
HDL workflow advisor internal error
Hope this is now resolved in R2020b release. If not please share reproduction steps. kiran.kintali@mathworks.com

12 days ago | 0

Answered
Is there a Rand() function alternative for HDL Coder?
Please check the attached example of uniform rand number generation using HDL Coder native floating point code generaiton featur...

12 days ago | 0

Answered
Struct in HDL Function
Great to know this. Thanks for sharing.

12 days ago | 0

| accepted

Answered
'Failed aType != nullptr' error during HDL code generation
The error is resolved in R2018b release.

13 days ago | 0

Answered
Adding of two signals and convert into vhdl
If you are using autoamted floating point to fixed point conversion tool please share the testbench. https://www.mathworks.com/...

13 days ago | 0

Answered
importhdl vector index operation
Please share functional verilog module to diagnose the error.

13 days ago | 0

Answered
Does the Specialized Power Systems toolbox work with HDL workflow advisor
SPS models need to be manually converted to single / double precision floating point models with underlying math before you run ...

13 days ago | 0

Answered
Struct in HDL Function
You may find this example useful. web(fullfile(docroot, 'fixedpoint/gs/manually-convert-a-floating-point-matlab-algorithm-to-fi...

13 days ago | 0

Answered
How to serialize vector data for HDL coder.
You can find some common techniques to create buffered data in this example. https://www.mathworks.com/help/hdlcoder/ug/image-e...

13 days ago | 0

Answered
matlab function block for HDL generate
HDL Coder automatically infers clock, clocken, reset from the model. The inputs to MATLAB function block are pure data inputs. ...

13 days ago | 0

Answered
hdl coder model checker output latetency and ulp error warning
These are messages informing about blocks that introduce latency. In case you have such blocks in feedback loops you need to tak...

13 days ago | 0

Answered
Fixed-Point Designer tells me that "Magnitude-Angle to Complex" Block is not supported. Why?
This issue is resolved in R2016b release.

13 days ago | 0

Answered
Simulink Spectrum Analyzer shows noise floor below max SQNR
https://www.mathworks.com/help/dsp/ref/spectrumanalyzer.html There are multiple settings that could affect the observed noise f...

16 days ago | 0

| accepted

Answered
errors with HDL verification # very with HDL test bench
What is the release you are currently running into this error? It looks like you are running into a HDL code generation issue. ...

17 days ago | 0

Answered
how translate stateflow variable to hdl std_logic_vector(0 to 7)
>> type compBoolVector.m function y = compBoolVector(u, v) y = all(u == v); >> >> a = true(1, 10); b = a; % create so...

19 days ago | 0

Answered
how translate stateflow variable to hdl std_logic_vector(0 to 7)
HDLCoder does not currently support such customization. Fixed Point types generate DOWNTO syntax, and arrays including array of ...

19 days ago | 0

| accepted

Answered
Is it possible to generate HDL code (VHDL) of a Simulink variant reference model in a way that the "active variant" is selectable through VHDL generics?
HDL Coder compiles away all the inactive variants and generates code only for the active variant. Can you share a sample model a...

24 days ago | 0

| accepted

Load more