Assuming that you are trying to generate the following GENERIC & GENERIC MAP in VHDL to pass to a subsystem with a BlackBox implementation:
COMPONENT blackbox
GENERIC( Sig1 : STD_LOGIC;
Sig2 : STD_LOGIC_VECTOR(3 DOWNTO 0)
);
-- snip --
u_blackbox : blackbox
GENERIC MAP( Sig1 => '0',
Sig2 => "0000"
)
where 'Sig1' is a single bit signal assigned a value of '0' and 'Sig2' is a 4-bit vector signal assigned a value of "0000".
The corresponding code to set the GenericList parameter for the Black Box subsystem in your model would be:
>> hdlset_param('blackbox_test/toplevel/blackbox','GenericList',...
'{{''Sig1'',''''''0'''''',''STD_LOGIC''},{''Sig2'',''"0000"'',''STD_LOGIC_VECTOR(3 DOWNTO 0)''}}');
Alternatively, you can open the HDL parameters for the Black Box subsystem and enter the following string into the block mask:
{{''Sig1'',''''''0'''''',''STD_LOGIC''},{''Sig2'',''"0000"'',''STD_LOGIC_VECTOR(3 DOWNTO 0)''}}
Notice that to generate the string '0', the 0 is enclosed by 6 single quotes each.
To insert a numeric value defined in another variable, use "num2str":
>> myGainValue = 33;
>> str = ['{{''gainValue'',''' num2str(myGainValue) '''}}'];
>> hdlset_param('blackbox_test/toplevel/blackbox','GenericList',str);
For more information on "GenericList" and other Black Box parameters, refer to the following documentation:
How to validate the value passed to 'GenericList':
First, create variable 'char' containing the value in base workspace (where two single quotes will be parsed to one single quote):
>> char = '{{''Sig1'',''''''0'''''',''STD_LOGIC''},{''Sig2'',''"0000"'',''STD_LOGIC_VECTOR(3 DOWNTO 0)''}}'
char =
'{{'Sig1','''0''','STD_LOGIC'},{'Sig2','"0000"','STD_LOGIC_VECTOR(3 DOWNTO 0)'}}'
And then evaluate the 'char' variable to get the cell array of character vectors:
>> genericsList = evalin('base',char);
>> genericsList{1,:}
ans =
1×3 cell array
{'Sig1'} {''0''} {'STD_LOGIC'}
ans =
1×3 cell array
{'Sig2'} {'"0000"'} {'STD_LOGIC_VECTOR(3 DOWNTO 0)'}