HDL Coder; Matlab Function Blocks and Clocked Processes

I belive my request is quite straigth forward.

I want the logic of my Matlab Funciton Block to be generated as clocked logic and not combinatorial logic.

Lets use the eml_hdl_incrementer example.

It generates

eml_inc_blk_1_output : PROCESS (ctr_preset, ctr_preset_val_unsigned, current_count)

But I would want it to generate

eml_inc_blk_1_output : PROCESS (clk)

I mean it should not be a miracle to achieve, but I could not find an option, that allows me to enforce this behaviour.

Is there an option to make matlab generate a clocked process or do I have to use specific patterns in my funciton?

Answer 1

[Kiran Kintali]

For a subset of MATLAB with data flow semantics you may find MATLAB Function Block (Data Path Architecture) more suitable for your coding style needs

hdlset_param('eml_hdl_incrementer_dp/DUT_eML_Block/eml_inc_blk', 'Architecture', 'MATLAB Datapath');

HDL Code

-- -------------------------------------------------------------
-- 
-- File Name: hdlsrc\eml_hdl_incrementer_dp\eml_inc_blk.vhd
-- Created: 2024-08-19 03:27:50
-- 
-- Generated by MATLAB 25.1, HDL Coder 25.1, and Simulink 25.1
-- 
-- -------------------------------------------------------------


-- -------------------------------------------------------------
-- 
-- Module: eml_inc_blk
-- Source Path: eml_hdl_incrementer_dp/DUT_eML_Block/eml_inc_blk
-- Hierarchy Level: 1
-- Model version: 30.1
-- 
-- The function incrementer implements a preset counter that counts
-- how many times this block is called. 
-- 
-- This example function shows how to model memory with persistent variables,
-- using fimath settings suitable for HDL. It also demonstrates MATLAB
-- operators and other language features that HDL Coder supports
-- for code generation from Embedded MATLAB Function block.
-- 
-- On the first call, the result 'counter' is initialized to zero.
-- The result 'counter' saturates if called more than 2^14-1 times.
-- If the input ctr_preset receives a nonzero value, the counter is 
-- set to a preset value passed in to the ctr_preset_val input.
-- 
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY eml_inc_blk IS
  PORT( clk                               :   IN    std_logic;
        reset                             :   IN    std_logic;
        enb                               :   IN    std_logic;
        ctr_preset                        :   IN    std_logic;
        ctr_preset_val                    :   IN    std_logic_vector(13 DOWNTO 0);  -- ufix14
        counter                           :   OUT   std_logic_vector(13 DOWNTO 0)  -- ufix14
        );
END eml_inc_blk;


ARCHITECTURE rtl OF eml_inc_blk IS

  -- Signals
  SIGNAL const_expression                 : unsigned(13 DOWNTO 0);  -- ufix14
  SIGNAL ctr_preset_val_unsigned          : unsigned(13 DOWNTO 0);  -- ufix14
  SIGNAL counter_1                        : unsigned(13 DOWNTO 0);  -- ufix14
  SIGNAL current_count                    : unsigned(31 DOWNTO 0);  -- uint32
  SIGNAL current_count_1                  : unsigned(31 DOWNTO 0);  -- uint32
  SIGNAL counter_2                        : unsigned(13 DOWNTO 0);  -- ufix14
  SIGNAL inc                              : unsigned(14 DOWNTO 0);  -- ufix15
  SIGNAL counter_3                        : unsigned(13 DOWNTO 0);  -- ufix14

BEGIN
  const_expression <= to_unsigned(16#0001#, 14);

  ctr_preset_val_unsigned <= unsigned(ctr_preset_val);

  -- store counter value for next iteration
  current_count <= resize(counter_1, 32);

  intdelay_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      current_count_1 <= to_unsigned(0, 32);
    ELSIF clk'EVENT AND clk = '1' THEN
      IF enb = '1' THEN
        current_count_1 <= current_count;
      END IF;
    END IF;
  END PROCESS intdelay_process;


  -- zero the counter on first call only
  counter_2 <= current_count_1(13 DOWNTO 0);

  -- otherwise count up
  inc <= resize(counter_2, 15) + resize(const_expression, 15);

  counter_3 <= inc(13 DOWNTO 0);

  
  counter_1 <= counter_3 WHEN ctr_preset = '0' ELSE
      ctr_preset_val_unsigned;

  counter <= std_logic_vector(counter_1);

END rtl;