Why do I receive a privimporthdl error when importing the operator.vhd example

Hello,

I am trying to import a VHDL file using the operator.vhd example. However, I receive the following error when using the importhdl function.

I beleive I have followed the example correctly, but I am at a loss as to why this is occuring. Is this a problem experienced by others at all? I'm not sure what I can try next.

Below is the operator.vhd code when it is opened within the MATLAB editor.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Operator is
    Port ( A : in  STD_LOGIC_VECTOR(3 downto 0);
           B : in  STD_LOGIC_VECTOR(3 downto 0);
           OpSelect : in STD_LOGIC_VECTOR(2 downto 0);
           Result : out STD_LOGIC_VECTOR(3 downto 0));
end Operator;

architecture Behavioral of Operator is
begin
    process(A, B, OpSelect)
    begin
        case OpSelect is
            when "000" => -- Addition
                Result <= A + B;
            when "001" => -- Subtraction
                Result <= A - B;
            when "010" => -- Bitwise AND
                Result <= A and B;
            when "011" => -- Bitwise OR
                Result <= A or B;
            when "100" => -- Bitwise XOR
                Result <= A xor B;
            when others => -- Default case
                Result <= not (A + B);
        end case;
    end process;
end Behavioral;

Answer 1

[Karanjot]

Hi Dan,

If you're encountering issues with importing a VHDL file using the importhdl function in MATLAB, a good first step is to inspect the entire stack trace provided by MATLAB. The error log often contains specific details that can help pinpoint the source of the problem.

MATLAB has certain limitations on the VHDL and Verilog constructs that can be imported. Hence, I recommend checking out the following documentation on supported Verilog constructs for HDL import:

https://www.mathworks.com/help/hdlcoder/ug/supported-verilog-constructs-for-hdl-import.html

While this page focuses on Verilog, it can give you a sense of the types of constructs that might be problematic.

If you find that your code uses unsupported features, consider modifying it to include supported constructs instead.

Hope this helps!

Answer 2

[Kiran Kintali]

VHDL Import is a new feature in R2024b release.

https://www.mathworks.com/help/releases/R2024b/hdlcoder/release-notes.html?startrelease=R2019b&endrelease=R2024b&rntext=&groupby=release&sortby=descending&searchHighlight=

Import VHDL code into the Simulink environment using importhdl function

You can now import synthesizable VHDL® code into the Simulink modeling environment. When you execute the importhdl function, the function analyzes the VHDL files and generates a corresponding Simulink model. This model visually interprets the VHDL code, showcases its functionality and behavior.

When you import the VHDL code, make sure that the constructs used in the HDL code are supported by importhdl function. For more information, see Supported VHDL Constructs When Generating Simulink Models from VHDL Code.

[Dan Lardner]

Hi Kiran,

Thanks for letting me know. I will try the .vhd import again after I have had a chance to read the release notes.

However, I did try import Verilog .v files and had a little more success, however it still failed. This was due inputs being tri-stated as shown below.

I was attempting to import Altera's Remote Update Core IP.

It does mention that INOUT ports are not supported on the Verilog constructs page below.

https://au.mathworks.com/help/hdlcoder/ug/supported-verilog-constructs-for-hdl-import.html

However, is there a way to move around this?

Regards,

Dan

[Kiran Kintali]

Hi Dan,

Thanks for the followup. The Verilog and the new VHDL importers are primarily helper tools and teaching utils on how to convert a synthesizable subset of the language that have equivalence in Simulink.

Please note that the tri-stated buffers, inout ports and several constructs in the language may not have Simulink equivalence. Please reach out to tech support with your additional requirements.

Thanks