How can I create an HDL Coder IP core that accesses multiple external memory locations with External DDR4 Memory Access?

Using HDL coder and HDL verifier toolboxes, targeting the Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit, I want to create an IP core that accesses multiple external memory locations (e.g. 4GB PS DDR4 & 512MB PL DDR4). However, when using the HDL Workflow Advisor tool on step 1.3 when defining the input and output ports I am only able to have one master read and write data and control channels.
How can I create an HDL Coder IP core that accesses multiple external memory locations with External DDR4 Memory Access?

Answer 1

[MathWorks Support Team]

If you use generic IP core generation ('Generic Xilinx Platform'), you can follow this documentation page to use "Add more ..." option to add additional AXI4 Master interface to the Target Interface choice.

Then you can generate a Xilinx IP core with more than one AXI Master interface. After that, you can drop the HDL Coder generated IP Core into a Vivado design, and connect two AXI Master interface to PS and PL DDR.

If you are using an IP core generation board and reference design workflow, you need to create a custom reference design that contain two AXI4 Master interface. To create a custom reference design that uses both PS and PL DDR, you need to modify your custom reference design in following steps:

1. For PL DDR, the Vivado block design need to contain the Xilinx Memory Interface IP, the DUT IP core AXI Master interface need to connect to the slave port of the Memory Interface IP
2. For PS DDR, the Vivado block design need to contain the PS IP, and the DUT IP core AXI Master interface need to connect to the HP slave port in the PS IP
3. In the custom reference design plugin_rd.m file, please add more than one hRD.addAXI4MasterInterface() method
4. In the device tree of the Linux image, a "reserved-memory" node also need to be added, so when DUT IP core access PS DDR, it will not conflict with the Linux OS running on ARM processor