what is the difference between FPGA Turnkey and IP Core Generation?
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In HDL Workflow advisor one could choose between different target workflows such as Generic ASICS/FPGA, FPGA Turnkey, IP Core Generation, FPGA-in-the-loop, Simulink real-time FPGA I/O. I have researched for almost half a day and I couldn't find a clear explanation of differences between these modes. In particular, I would like to know about difference between FPGA Turnkey and IP Core Generation. It is highly appreciated if someone briefly explain this, or cite references where this topic is discussed.
Best regards, Yashar
Wang Chen on 7 Aug 2015
Edited: Wang Chen on 7 Aug 2015
Both IP Core Generation and FPGA Turnkey workflows can help you prototype your Simulink/MATLAB algorithm on FPGA/SoC boards.
IP Core Generation workflow adopts the IP-centric design methodology. You can generate your own custom HDL IP core from your Simulink/MATLAB algorithm. This custom IP core is sharable and reusable, and also comes with a generated IP core report.
You can then integrate the generated IP core into a larger design in FPGA design tools such as Altera Qsys, or Xilinx Vivado/IP Integrator. You can also register your Vivado/Qsys project as a custom reference design, so the IP Core Generation workflow can help you integrate the IP core into the reference design automatically.
FPGA Turnkey workflow does not use the IP-centric design methodology. Instead, it generates the HDL codes for the whole FPGA design, including the algorithm HDL code, the FPGA top level wrapper HDL code, and FPGA Pin mapping constraints, so you can run your algorithm on standard alone FPGA board. FPGA Turnkey workflow targets FPGA boards only, it does not support Zynq/Altera SoC boards