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filWizard: Error during Validation of Altera Stratix IV GX 230 FPGA development kit

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THOUMY François
THOUMY François on 27 Apr 2017
Commented: xioabo li on 26 Nov 2020
I'm trying to use filWizard to connect Matlab to a Altera Stratix IV GX 230 FPGA development kit board via Ethernet.
When I run the FPGA-in-the-loop-test to validate the connection, I get the following messages:
Starting FPGA-in-the-Loop test ...
Generating FPGA programming file ...Passed
Programming FPGA ...Passed
Checking Ethernet connection ...Passed
Running FIL simulation ...Failed
Error:Did not receive version information from the hardware. You must have a valid connection, a compatible development board, and compatible versions of the block and FPGA programming file.
My configuration is the following:
Quartus 16.1
Matlab R2017A with HDL Verifier toolbox
PC IP config 192.168.0.2
Board address 192.168.0.1
PC and board connected through a crossed cable (I also tried with a switch).
I'm using a Quartus licence given with the Altera development kit, then the IP core related to Ethernet is time limited (Info (115017): Design contains a time-limited core -- only a single, time-limited programming file can be generated).
Could it be the cause of the issue ?
Thanks for any help

Answers (3)

Tao Jia
Tao Jia on 28 Apr 2017
I think your guess might be correct. We do use the Altera Etherent SGMII to GMII IP in your setup. It requires an additional Altera license to work properly.
You can try to use Altera Quartus programmer to program FPGA with the auto generated sof file. It will have a command-line window opened at the end. You'll need to make it remain open to make the FPGA to continue working.
Another option is to try the JTAG interface which does not require any licensed Altera IP.
Hope this helps, Tao

THOUMY François
THOUMY François on 5 May 2017
Thanks for the answer. In fact I succeeded to make it work after many trials. Connecting the PC to the board by a straight cable, after resetting (by S1) the board (not only On/off). So it can work without an Altera Ethernet IP core licence. If there is no licence, the tool outputs a time limited .sof which works properly only 1 hour after the FPGA programming.

Hoan Tran
Hoan Tran on 4 Oct 2017
Edited: Hoan Tran on 4 Oct 2017
Hi, Im getting the same problem, although I passed the FPGA-in-the-loop validation and loading bitstream successfully to development kit, I get the following error when I run FIL Simulink model.
"did not receive version information from the hardware. you must have a valid connection, a compatible development board, and compatible versions of the block and fpga programming file"
My configuration is:
Matlab R2016a/
Quartus Prime 16.0 Standard and also try Quartus 13sp1/
Altera Stratix IV GX 230 FPGA/
Jtag connection/
Thanks for your help

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