I'm trying to use filWizard to connect Matlab to a Altera Stratix IV GX 230 FPGA development kit board via Ethernet.
When I run the FPGA-in-the-loop-test to validate the connection, I get the following messages:
Starting FPGA-in-the-Loop test ...
Generating FPGA programming file ...
Programming FPGA ...
Checking Ethernet connection ...
Running FIL simulation ...
Error:Did not receive version information from the hardware. You must have a valid connection, a compatible development board, and compatible versions of the block and FPGA programming file.
My configuration is the following:
Matlab R2017A with HDL Verifier toolbox
PC IP config 192.168.0.2
Board address 192.168.0.1
PC and board connected through a crossed cable (I also tried with a switch).
I'm using a Quartus licence given with the Altera development kit, then the IP core related to Ethernet is time limited (Info (115017): Design contains a time-limited core -- only a single, time-limited programming file can be generated).
Could it be the cause of the issue ?
Thanks for any help